# Improving Soc Power Management and Clock Generation Using a Delta-Sigma Fractional-N PLL

@head: Inherent Benefits of a Delta-Sigma Fractional-N PLL in Power-Conscious SoC Designs

@deck:This paper compares and contrasts two types of PLLs, highlighting the benefits designers can exploit by using fractional PLLs in place of traditional integer solutions for system clocks.

@text: The hardworking, humble PLL has long served as a sort of "heart" of an IC, generating clocks within the chip to deliver frequencies for each application.Most SoC designs use multiple PLLs to generate the frequencies required when integration of components occurs.Examples of SoCs using these PLLs include microprocessors, USB, memory interfaces (DDR), audio, and video frequencies.The integer PLL has long served this function. More recently, however, fractional PLLs are being used to generate multiple frequencies from one clock (crystal) source.This paper will compare and contrast these two types of PLLs, highlighting the benefits designers can exploit by using fractional PLLs in place of traditional integer solutions for system clocks.

**<b>Integer PLLs</b>**

Today, most designs use an M/N integer PLL to generate on-chip frequencies.A basic block diagram of an integer PLL is shown in <i>Figure 1</i>.The input frequency is multiplied by the ratio of the feedback divider (M) to the pre divider (N) to generate the VCO output frequency.

Figure 1: Integer PLL

The M/N multiplier cannot always generate the desired frequency with sufficient accuracy.For those cases, two integer PLLs may be cascaded together asillustrated in <i>Figure 2</i>.

Figure 2: Integer PLL cascade

For a cascaded integer PLL, the input frequency is first multiplied by M1/N1 and then by M2/N2.While this technique may get to the desired frequency or close to it, it suffers from some drawbacks as follows:

<ul>

<li>It is not easy to figure out the M and N values that meet the VCO range and input range in some solutions.Take, for example, the following design: Input frequency is 27 MHz; desired output frequency is 24.576MHz. The multiplier and divider to get the output frequency is 3072/3375 – determining these numbers while staying in range of each VCO (typically 2:1) is cumbersome or simply not possible.</li>

<li>This integer cascade adds significantly to design overheads – it draws 2× the area and power and has 1.4× larger long term jitter than a single PLL.</li>

<li>Integer cascades make it more difficult to change settings on the fly without causing frequency swings.</li>

</ul>

**<b>Fractional PLLs</b>**

Until recently, cascaded integer PLLs were the only solution available to chip designers. Fractional PLLs are now readily available. As the name implies, the fractional PLL multiplies by an integer and a fraction. The fraction value is generated by continuously changing the feedback divider. For example, if the feedback divider alternates between dividing by 11 and 12, then the output frequency would be 11.5 times the input frequency. By changing the number of times, you divide by 11 or 12 you can generate fractions between 11 and 12.

A drawback of this technique is the potential to generate sidebands or spurs at the frequency the divider is being switched. When the divider alternates between 11 and 12 every reference period, for example, the spur would occur at 1/2 of the reference frequency. These spurs are undesirable in digital systems because they can cause unwanted interference with other circuitry on-chip.

The problem of increased jitter can also arise when the desired fraction is close to 0 or 1 because the switching cycle becomes very long.This moves the fractional noise to low frequencies, which the PLL cannot filter effectively. If the desired fraction is 11.01, for example, the PLL would divide by 11 ninety nine times and 12 one time.The fractional noise would then be at 1/100 of the reference frequency that is likely well below the loop bandwidth and would show up directly as jitter on the output.

In order to reduce the effects of these problems, a delta-sigma modulator can be used.A delta-sigma modulator shifts the noise to high frequencies allowing it to be easily filtered out by the PLL, by rapidly switching between multiple divide values with the average divide value still being the correct fraction. When a delta-sigma modulator with a 3-bit quantizer is used to generate 11.01, for example, the feedback divide may take on any value from 8 to 14.In addition, the divider never stays at the same setting for more than a few cycles that keeps the switching cycle short and hence the noise at high frequencies.

Another benefit can be obtained by adding a small amount of pseudo-random noise to the modulator.This spreads out and reduces the fractional spurs by preventing the divider from entering limit cycles where the same pattern repeats in a short amount of time.Spurious tones can be made arbitrarily small with a delta-sigma modulator by increasing the length of the pseudo-random noise pattern.

A delta sigma fractional-N PLL block diagram is shown in <i>Figure 3</i>.

*Figure 3: Delta-Sigma Fractional-N PLL*

The basic structure of a fractional PLL is the same as the integer one; however, a delta-sigma modulator is added to generate the fractional multiplier. The number of fractional bits may vary anywhere from 16 to 24 bits. Increasing the number of bits increases the precision of the fractional value. For example, a 16-bit fraction will give five places to the right of the decimal point and 24 bits will give eight decimal places of fractional precision. With a fractional PLL, sub hertz and sub PPM accuracy and step size can easily be achieved.

Using the previous example of a 27MHz input and a 24.576MHz desired output, a fractional PLL would yield a more elegant solution (as compared to cascaded integer PLLs) – using a fractional multiplier of 12.74312 with a post divider of 14, a single fractional PLL would yield a final output frequency of 24.576004MHz.

**<b>Application Example</b>**

Let's look at a sample scenario for a typical, low power SoC application, which includes a microprocessor clock, SRAM, Flash, DSP, I/Os and USB. Other assumptions in this example include the following:

<ul>

<li>The microprocessor and memory clocks can be modulated.</li>

<li>There is a desire to use a low cost 24 MHz crystal to save cost.</li>

<li>The optimal clock frequency is 125MHz.</li>

</ul>

Because an integer PLL can only multiply by whole numbers, it is impossible in this example to obtain the desired clock frequency by using a single integer PLL. Either you would have to sacrifice power and multiply by 6 to generate 144MHz, or you would need to sacrifice performance and multiply by 5 to achieve 120MHz. Other options using an integer PLL would be to use a PLL cascade and achieve the desired output at an increase in area and power, or to use a higher cost crystal.

In contrast, by using one fractional PLL, you could multiply by 5.20833 and achieve the 125MHz output required. This saves 19 MHz versus the integer 144 MHz solution, yielding 13% lower power without a performance sacrifice and enables use of a low cost, standard crystal to optimize BOM costs.

Fractional PLL power tends to be lower than the integer PLL because the integer PLL tends to use a higher VCO frequency. Also, fractional PLLs have better long-term jitter because M/N integer PLLs divide the input frequency down, which forces the PLL bandwidth to be reduced and hence allows more wander.A fractional PLL that does not need to divide the input frequency can frequently use a higher loop bandwidth to suppress long term jitter.

Another key benefit of using a fractional PLL is that its fine grain frequency control abilities allow late design-cycle or post-silicon adjustments to accommodate hardware or software induced changes. Should testing reveal the processor can only run at 115MHz, for example, a designer can simply reprogram the fractional PLL to multiply by 4.70167. By contrast, reprogramming the integer PLL to multiply by 4 to achieve 96MHz would significantly impact the performance of the design. In this example, changing the crystal frequency is not an option because other blocks in the chip use a multiple of this frequency.

**<b>Generating Multiple Frequencies with One Crystal</b>**

Often, in order to achieve the fine-grain control needed by the chip, several integer PLLs are cascaded together for each clock function. This is done to eliminate the issues inherent in dividing by an integer. While cascading integer PLLs continues to be a viable solution, generating multiple output frequencies from one crystal can have drawbacks in area and power and be difficult to implement. Using a fractional PLL allows designers to use lower cost crystals to achieve the desired results. As is illustrated in <i>Figure 4</i>, a single 27MHz crystal is used to generate four common audio frequencies. The fractional PLL generates a fractional frequency that is then divided to produce the desired frequencies. Creating this same scenario using an integer PLL solution could require several cascaded integer PLLs at a cost of increased area, power, and jitter.

*Figure 4: Generating Multiple Frequencies with a Fractional PLL*

Unlike traditional integer PLLs, the delta-sigma fractional-n PLL inherently supports any frequency in, delivers any frequency out, and can do so without needing to cascade PLLs. This can reduce the Bill of Materials for a product by being able to generate any frequency with one clock source. Using a delta-sigma fractional-n PLL in place of the more traditional integer PLL can reduce or eliminate the power and area concerns.

**<b>Jitter Considerations</b>**

There has been concern about jitter in a fractional PLL based on the historical fact that – by design – a fractional PLL may have more noise or tones in the clock spectrum. However, in newer generation designs this noise does not necessarily translate to increased jitter. A well-designed delta sigma fractional PLL with a second- or third-order loop can shape noise to a higher frequency that is well outside the loop bandwidth and can be filtered to levels far below other noise contributors.

Since VCO noise is equivalent in both integer and fractional designs, it is not a consideration in the comparison. In addition, a fractional PLL can operate with a higher input clock, without pre-divide, enabling lower long-term jitter. Traditionally, integer PLLs require an input frequency to bandwidth ratio of around 15:1 in order to maintain stability. Increasing this ratio by just a factor of 3 to 50:1, can completely suppress delta-sigma noise leaving only the noise sources that are common to both integer and fraction PLLs. Therefore, for any integer solution that requires a pre-divide of more than 3, a fractional PLL is likely to meet or exceed the jitter performance of its integer counterpart. (See the <i>Jitter Terminology</i> topicat the end of this paper for reference information.)

**<b>Summary</b>**

Fractional PLLs provide many advantages over traditional integer PLLs.

<ul>

<li>A fractional PLL can generate any frequency from one crystal

<ul<li>True fractional multiplication</li>

<li>Integer PLLs can only do × 2, 3, 4, 5, 6, 7…. ~128. For fractions, an additional external input divider, which increases jitter, is added or two or more M/N PLLs are cascaded.The integer PLL cascade has 2× area and power and ~1.4× higher LTJ.</li</ul</li>

<li>Fractional-N multiply maximizes silicon performance

<ul<li>If the final IC runs a bit faster or slower than intended – the Delta Sigma Fractional PLL gives the exact frequency desired maximizing software headroom or chip yield.</li</ul</li>

<li>The Delta Sigma Fractional PLLdelivers the exact frequency, reducing power by 10% to 20% compared to an Integer PLL

<ul<li>Integer PLL with 24MHz input can supply 1×, 2×, . . . 5×, 6×, which results in either 120MHz (5x) or 144MHz (6x).</li>

<li>Fractional PLL can supplythe exact frequency reducing power for the same performance; 125 MHz saves 19 MHz or about 13% lower power.</li</ul</li>

<li>A fractional PLL enables small PPM-level frequency adjustments.

<ul<li>Adjust oscillator temperature drift – e.g. BTS base station</li>

<li>Transmitter-receiver clock mismatch – e.g. MPEG</li>

<li>Calibrate and compensate a low cost ceramic resonator</li</ul</li>

</ul>

A brief summary of additional comparisons between fractional and integer PLLs is provided in <i>Table 1</i> below.

Integer / FractionalMultiplication step size / Multiple of input frequency

0 to ± 1000ppm / Very small

0 to ± 1ppm

Frequency generation / Some solutions require cascaded PLLs

- Difficult to program

- 2x the area and power

- 1.4x the long term jitter / One PLL

Rate matching / DAC and external VCXO (voltage controlled crystal oscillator) / Adjust the fractional multiplication bits

Compensate for oscillator temperature drift / DAC and external VCXO / Adjust the fractional multiplication bits

*Table 1. Comparison of Integer and Fractional PLLS*

While SoC designs are providing challenges to designers, use of advanced technologies such as the delta sigma fractional-n PLL with its inherent flexibility can speed design cycles, improve power (or yields) and optimize performance for today's crop of consumer and mobile devices without sacrificing jitter performance.

**<b>References</b>**

<ol>

<li>Howard, Andy. <a href=" target="_new">Delta-Sigma Modulator PLLs with Dithered Divide-Ratio</a>.</li>

<li>Descleves, Cyril.<a href=" target="_new">Efficient Simulation Techniques for Modulated Delta-Sigma Fractional-N Synthesizers</a>.</li>

</ol>

**<b>PLL Jitter Terminology</b>**

<ul>

**<li<b<i>Period Jitter</i</b>**(PJ) – This is a measure of how much the non-adjacent periods of the clock change over the longer term. PJ is usually measured over 10,000 cycles of the output clock. PJ can be measured as Peak-to-Peak or by Root Mean Square (RMS). The shortest output clock period should be used to calculate the timing margin in synchronous circuits clocked by the PLL output.</li>

**<li<b<i>Cycle to Cycle Jitter, Adjacent Cycle Jitter or Short Term Jitter</i</b>**(C2CJ or STJ) – C2CJ is a measure of how much the output period changes from one cycle to the next and affects the timing margin for some digital circuits clocked by the PLL output. Short Term Jitter is commonly defined to be the distribution of differences between cycle times of adjacent cycles, measured either on rising or falling clock edges. This may be seen as an instantaneous frequency shift by core logic.</li>

**<li<b<i>Long Term Jitter</i</b>**(LTJ or Accumulated jitter) – This is a measure of how much the PLL output clock edge deviates from the position of an ideal clock over a longer term. PLL LTJ is usually measured over 10,000 cycles of the output clock. A low LTJ indicates a very stable PLL with loop filter cutoff well below the input reference frequency. LTJ is seen as a frequency shift by core circuits. LTJ degrades I/O circuits setup and hold timings. When outputs from two independent PLLs are used, LTJ can also indicate the maximum drift or difference in timing between circuits clocked from the two PLLs.

</ul>

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@author: Dan Hillman, vice president of engineering for the semiconductor IP division of <a href=" target="_new">MOSAID Technologies</a>, has more than 25 years experience in chip engineering and extensive development and management experience in the semiconductor, computer and EDA industries. Hillman spent 11 years at Apple Computer as a hardware manager directly involved in the design of the Apple IIGS, Macintosh and Newton. He began his career at RCA and Zilog corporations.Hillman holds a BS in Electrical Engineering from PurdueUniversity.