Double Edge Triggered Flip-Flop with 45Nm CMOS Technology
Double Edge Triggered Flip-flop with 45nm CMOS Technology
B.Sreekanth Reddy, R.Mallikarjuna Reddy, Kuppam N Chandra Sekhar
Abstract— The power consumption of a system is a crucial parameter in modern VLSI circuits especially for low power applications. In this project, a low power and high performance Double Edge Triggered D-Flip Flop (DETFF) design is proposed in 45nm CMOS technology. The proposed DETFF is having less number of transistors than earlier designs. The novelty of the proposed flip flop lies in the feedback strategy using common feedback inverter and pass transistors in the place of transmission gates to make the design in static with less number of transistors. This improves the power efficiency of the proposed flip flop. Simulations are carried out using HSPICE tool with different clock frequencies ranging from 400MHz to 2GHz and with different supply voltages ranging from 0.8V to 1.2V.
In general, a power delay product (PDP) based comparison is appropriate for low power portable systems. At nominal condition, the PDP of the proposed DETFF is improved by 65.48% and 44.85% over earlier designs DETFF 1 and DETFF 2 respectively. Simulation results show lowest power dissipation and least delay than existing designs, which claims that the proposed DETFF is suitable for low power and high speed applications.
Index Terms—CMOS, flip-flops, Double-edge triggered, power dissipation, delay and PDP.
INTRODUCTION
Very Large Scale Integration (VLSI) is the methodology of making coordinated circuits by joining a huge number of transistors into a solitary chip. VLSI started in the 1970s when complex semiconductor and correspondence innovations were being produced. The chip is a VLSI gadget.
The principal semiconductor chips held two transistors each. Ensuing advances included more transistors, and as an outcome, more individual capacities or frameworks were incorporated about whether. The initially coordinated circuits held just a couple of gadgets, maybe upwards of ten diodes, transistors, resistors and capacitors, making it conceivable to create one or more rationale entryways on a solitary gadget. The little scale joining (SSI), changes in system prompted gadgets with many rationale doors, known as medium-scale mix (MSI).
R.Mallikarjuna Reddy, ECE Department, Jawaharlal Nehru Technology University,GVIC College, Madanapalle,Andhra Pradhesh, INDIA,Mobile:8096330172., email:
B.Sreekanth Reddy ,ECE Department Name, Jawaharlal Nehru Technology University,GVIC College,Madanapalle,Andhra Pradhesh ,INDIA,Mobile:9492854133.,e-mail:
Kuppam N Chandra Sekhar, ECE Department, Jawaharlal Nehru Technology University,GVIC College,Madanapalle,Andhra Pradhesh ,INDIA,Mobile:9885229501, e-mail: .
Further changes prompted expansive scale combination (LSI), i.e. frameworks with in any event a thousand rationale entryways. Current engineering has moved far past this imprint and today's chip have numerous a huge number of entryways and billions of individual transistors known as "Vast Scale Integration (VLSI). This is the field which includes pressing more rationale gadgets into littler and more diminutive ranges.
1.1.History and Evolution of VLSI:
The history and evolution of VLSI is given below.
At one time, there was an exertion to name and adjust different levels of substantial scale reconciliation above VLSI. Terms like Ultra-huge scale Integration (ULSI) were utilized. At the same time the enormous number of entryways and transistors accessible on regular gadgets has rendered such fine qualifications debatable. Terms recommending more noteworthy than VLSI levels of mix are no more in boundless utilization. Indeed VLSI is currently sort of curious, given the regular presumption that all microchips are VLSI or better.
Starting early 2008, billion-transistor processors are industrially accessible, a case of which is Intel's Montecito Itanium chip. This is relied upon to wind up more regular place as semiconductor manufacture moves from the current era of 65 nm methods to the following 45 nm eras (while encountering new difficulties, for example, expanded variety crosswise over procedure corners).
1.2.Structured Design and difficulties
Organized VLSI configuration is a particular technique began via Carver Mead and Lynn Conway for sparing microchip region by minimizing the interconnect fabrics zone. This is gotten by monotonous course of action of rectangular macro pieces which can be interconnected utilizing wiring by projection. Organized VLSI configuration had been famous in the early 1980s, yet lost its prevalence later due to the approach of arrangement and steering instruments squandering a considerable measure of territory by directing, which is endured in view of the advancement of Moore's Law.
Moore's Law:
Moore's law depicts a long haul incline ever. The quantity of transistors that can be put reasonably on an incorporated circuit duplicates roughly at regular intervals indicated in figure 1.1. This pattern has proceeded for more than a large portion of a century and is relied upon to proceed until 2015 or 2020 or later.
Fig 1.1.Moores Law
Challenges
As chip configuration get to be more mind boggling because of innovation scaling, the planners have experienced a few difficulties which compel them to think past the outline plane, and look ahead to post-silicon:
Power utilization/Heat dissemination
As limit voltages have stopped to scale with propelling procedure engineering, element power dissemination has not scaled relatively. Keeping up rationale unpredictability when scaling the configuration down just implies that the force dissemination for every zone will go up. This has offered ascent to procedures, for example, dynamic voltage and recurrence scaling (DVFS) to minimize general force.
Process variety
As photolithography strategies tend closer to the essential laws of optics, accomplishing high precision in doping focuses and scratched wires is getting to be more troublesome and inclined to lapses because of variety. Fashioners now must mimic crosswise over different creation methodology corners before a chip is affirmed prepared for generation.
Stricter configuration tenets
due to lithography and engraving issues with scaling, outline standards for format have gotten to be progressively stringent. Planners must remember always of these standards while laying out custom circuits. The overhead for specially craft is currently arriving at a tipping point, with numerous configuration houses picking to switch to electronic outline mechanization (EDA) devices to mechanize their outline process.
Timing/outline conclusion
As clock frequencies have a tendency to scale up, planners are thinking that it more hard to disseminate and keep up low clock skew between these high recurrence tickers over the whole chip. This has prompted a climbing enthusiasm toward multi center and multiprocessor architectures, since a general speedup can be acquired by bringing down the clock recurrence and circulating transforming. CMOS gadgets have scaled descending forcefully in every innovation era to accomplish higher coordination thickness and execution
II LITERATURE SURVEY
2.1.Power Dissipation:
It is more advantageous to discuss power scattering of computerized circuits as of right now. Despite the fact that power depends significantly on the circuit style, it can be partitioned, when all is said in done, into static and element power. The static force is created because of the DC predisposition current, or because of spillage momentums. In the majority of the rationale families aside from the push-force sorts, for example, CMOS, the static power has a tendency to rule. That is the motivation behind why CMOS is the most suitable circuit style for substantial scale joining (VLSI).
High pressing thickness
Despite the fact that CMOS has points of interest, however when the CMOS circuit is utilized as a part of cutting edge advanced coordinated circuits, power utilization can be credited to four principle segments:
Pavg = Pdynamic + Pstatic + Psc + Pleakage
Fig 2.1: Sources of Power Dissipation in CMOS Circuits
The above mathematical statement comprises of four terms and thus represents that there are four significant wellsprings of force utilization in an advanced CMOS circuits. The main term speaks to the exchanging part of force, the second term speaks to the static force. The third term speaks to the short out force is brought on by the immediate way in the middle of VDD and ground, i.e. impede Isc, The fourth term is spillage power. The figure 2.1 demonstrates the wellsprings of force dissemination in CMOS circuits.
Static Power
Strictly talking, advanced CMOS circuits shouldn't devour static force for steady static current stream. All non-spillage present in CMOS circuits ought to just happen in homeless people when signs are exchanging. However there are times when deviations from CMOS style circuit configuration are essential, a sample of which is pseudo NMOS rationale circuit. Static force dissemination relies on upon a current stream from force to ground amid perfect time dissimilar to short out force scattering, which happens just amid exchanging movement. NMOS circuits indicate high static force utilizations on the grounds that power is associated straightforwardly to ground when entryways yield is rationale zero. In decently outlined and low power CMOS plans, static force ought to be zero.
The short out present ISC, which is emerges when both the NMOS and PMOS transistor systems are at the same time dynamic or on, directing present from the supply voltage VDD to ground. The force dispersal because of short out present Isc is known as short out force dissemination, PSC given by
Psc = IscVdd
2.2 Power Reduction Techniques
The following are some of the techniques to reduce power dissipation.
Reduction of Power Supply
The energy and power consumed by the CMOS digital circuits are sensitive to the power supply voltage as given by the following equations.
Energy, E = CVDD2
Power, P = CVDD2f
Reducing the power supply voltage is an efficient approach to lower the energy and power. The power supply voltage is actually the most crucial factor in reducing energy/ power. This will, however, be at the expense of the delay of the circuits. Using the Power Delay Product (PDP) as a metric, one can derive the optimum supply voltage that would yield minimum PDP.
The optimum supply voltage (for minimum PDP) can be found from the below equation and is given by
The above expression is valid for long-channel and deep sub micrometer devices. For long-channel transistors (α = 2), the optimum supply voltage is equal to 3VT, For deep sub micrometer devices with α closer to unity the optimum voltage is expected to be less than 3VT. For example, if α = 1.5, then VDD (OPT) = 2VT. At any rate, the optimum value for VDD is proportional to the threshold voltage. So, the conclusion is that the supply voltage must be reduced to minimize the PDP. Scaling the supply voltage below the point of minimum PDP will cause severe degradation in the delay. The second point is that the optimum supply voltage is related to the threshold voltage.
Reduction of Switching Activity
Another approach to low-power design is to reduce the switching activity and the amount of the switched capacitance to the minimum level required to perform a given task. Switching activity in CMOS digital integrated circuits can be reduced by algorithmic optimization and architecture optimization. Each of these aspects will be discussed briefly as below.
Algorithmic Optimization
Algorithmic optimization depends heavily on the application and on the characteristics of the data, such as the dynamic range, the correlation, and statistics of the data transmission and so on. Some of the techniques apply only to applications such as digital Signal Processing (DSP) and cannot be used for general-purpose processing.
Several architectural techniques have been proposed to reduce the switching activity, such as, ordering of the input signals and delay path balancing to remove glitching. In multi-level logic circuits, the propagation delay from one logic block to the next can cause spurious signal transitions or glitches, as a result of critical races or dynamic hazards occurs.
Reduction of Switched Capacitance
The amount of switched capacitance plays a significant role in the dynamic power dissipation of the circuit. Hence, the reduction of this parasitic capacitance is a major goal for low-power design of digital integrated circuits. The switching capacitance can be broken down into two categories, the first category is capacitance in dense logic (which includes the transistor parasitic and wire capacitances at the output of the gates) and the second category is capacitances of the busses and a clock network (which is mainly the wire capacitance). In some systems, the capacitance of the busses and a clock network may comprise close to 50% of the overall chip capacitance. An example of such system is the Alpha chip.
At the system level, one of the approaches to reduce the switched capacitance is to limit the use of shared resources. A simple example is the use of a global bus structure for the data transmission between a large numbers of operational modules. The type of logic style used to implement a digital circuit also affects the physical capacitance of the circuit. The physical capacitance is a function of the number of transistors that are required to implement a given function. For example, one approach to reduce the physical capacitance is to use transfer gates over conventional CMOS logic gates to implement logic functions.
3.2 INTRODUCTION TO FLIP-FLOPS
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The main difference between latches and flip-flops is that for latches, often called level-sensitive because their outputs are constantly affected by their inputs as long as the enable signal is asserted. They are transparent during the entire time when the enable signal is asserted. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.
D Latch with Enable
The D latch can also have an enable input as shown in figure 2.2. When the E input is asserted (E = 1), the Q output follows the D input. In this situation, the latch is said to be “open” and the path from the input D to the output Q is “transparent”. Hence the circuit is often referred to as a transparent latch. When E is de-asserted (E = 0), the latch is disabled or “closed”, and the Q output retains its last value independent of the D input. A sample timing diagram for the operation of the D latch with enable is shown in figure 3.2(d). Between t0 and t1, the latch is enabled with E = 1 so the output Q follows the input D. Between t1 and t2, the latch is disabled, so Q remains stable even when D changes.
Fig 3.2: D latch with enable (a) circuit using NAND gates (b) truth table(c) logic symbol (d) timing diagram
3.2.1 Flip-Flop Types
There are basically four main types of flip-flops: SR, D, JK, and T. The major differences in these flip-flop types are in the number of inputs they have and how they change state. The flip-flops can be described fully and uniquely by its logic symbol, characteristic table, characteristic equation, state diagram, or excitation table, and are summarized in figure 3.3.
Fig 3.3: Flip-Flop types
3.2.2 D Flip-Flop
The D flip-flop with positive-edge-triggered is shown in figure 3.3. Here two D latches are connected in series and a clock signal Clk is connected to the E input of the latches, one directly, and one through an inverter. The first latch is called the master latch. The master latch is enabled when Clk = 0 and follows the primary input D. When Clk is a 1, the master latch is disabled but the second latch, called the slave latch, is enabled so that the output from the master latch is transferred to the slave latch. The slave latch is enabled all the while that Clk = 1, but its content changes only at the beginning of the cycle, that is, only at the rising edge of the signal because once Clk is 1, the master latch is disabled and so the input to the slave latch will not change.
The circuit of figure 3.4(a) is called a positive edge-triggered flip-flop because the output Q on the slave latch changes only at the rising edge of the clock. If the slave latch is enabled when the clock is low, then it is referred to as a negative edge-triggered flip-flop. The circuit of figure 3.4(a) is also referred to as a master- slave D flip-flop because of the two latches used in the circuit. Figure 3.4(b) and figure 3.4(c) show the truth table and the logic symbol respectively.
Fig 3.4: Master-slave positive-edge-triggered D flip-flop: (a) circuit using D latches
(b) truth table (c) logic symbol
The edge triggered flip-flops can be classified into two types. As given below
- Single Edge Triggered Flip-Flop (SETFF)
- Double Edge Triggered Flip-Flop (DETFF)
In SETFF the data is sampled at only one edge either positive or negative edge, where as in DETFF the data is sampled at both edges.
3.3 SINGLE EDGE TRIGGERED FLIP-FLOP
The figure 3.5 compares the different operations between a latch and a flip-flop. In figure 3.5(a) a gated D latch, a positive-edge-triggered D flip-flop and a negative-edge-triggered D flip-flop, all having the same D input and controlled by the same clock signal. Figure 3.5(b) shows timing diagram of gated D latch, a positive-edge-triggered D flip-flop and a negative-edge-triggered D flip-flop.