Experiment #7
Analog-Digital Applications
In this experiment you will study analog-digital conversion techniques. You will prepare particular designs and implement useful test procedures for performance evaluations.
Part A. D/A Converter (R-2R converter & weighted resistor D/A converter)
In this part of the experiment you will design and test D/A converters: A 4-bit R - 2R Ladder D/A Converter and a weighted resistor D/A converter. The ladder D/A is shown below
When a bit is “1” the bit line is connected to VR. When a bit is “0” the bit line is connected to zero volts (ground).
The weighted resistor D/A is drawn below:
Part A. D/A Converter (Continued)
When a bit is “1” the bit line is connected to VR. When a bit is “0” the bit line is connected to zero volts (ground).
The D/A converters must be designed to provide a voltage output that is proportional to the binary number value (unsigned) of the 4-bit binary word input. Specifically, for the R - 2R Ladder D/A Vout = W/5V, and for the weighted-resistor D/A Vout = -W/5 V, where W is the input binary word value, which takes values over the range 0 - 15 (base 10). For example for the R-2R D/A the binary input 00002 should produce the value 010, 11112 should produce the value 1510, etc. For each D/A you should be able to design the circuits to use only one op-amp. This suggests that you will want to modify the design for the R-2R D/A shown in Figure 1 to bring the input into the + terminal of the op-amp. Standard TTL devices will drive the inputs to your D/A and thus, you should design for your inputs to either D/A to accept standard TTL conventions for logical 0 and 1 values.
In practice, we frequently do not mind if the D/A output is offset some small amount or does not quite have normal gain, since we can easily compensate for these irregularities. In this case output is given as:
Vout = Voff + G * W
Voff and G are estimated by plotting Vout versus W (16 points) and finding a “best fit” straight line (least squares criterion is frequently used). The errors between the best-fit line and actual values are referred to as relative linearity errors. Include in your tests of the D/A, evaluations of Voff and G and also an evaluation of relative linearity errors for your D/A. Gather the data necessary for this evaluation by using the digital oscilloscope to record data. Use your 4-bit counter chip to dynamically change W. Record the value of Vout as W is changed. Use Excel to do a least squares fit to the data and find Voff and G. Observe and record the effects of increased counter clock rate on the relative linearity and time response of each D/A. A useful measure of D/A “speed“ is the settling time, which is usually defined as the time required to respond to a voltage change produced by the least significant bit (LSB). Certain input transitions produce shorter settling times than others. We usually specify the worst case settling time as the D/A’s settling time specification. Determine the worst case input transition(s) for the D/A and measure the worst case settling times for each D/A. If you look carefully you will see two speed limitations. The D/A takes a small amount of time to respond to most changes of the LSB. (How small is that time?) A longer period of time is required for one particular transition. Which transition requires the longest amount of time? What is responsible for the long “settling” time associated with this transition?
Updated April 6, 2005
Part B. Parallel A/D Converter
Successive approximation A/D (analog to digital) converters estimate a digital approximation by searching among appropriate digital words for the best estimate. Each candidate digital word is compared to the analog input after a D/A conversion. Using a binary search scheme the successive approximation A/D finds its estimate in roughly log2n comparisons (n is the digital word length in bits). For some applications this process is to slow. A fundamentally faster approach is outlined in Figure 2. Here we perform many comparisons in parallel; thus we call this a parallel A/D converter. In this scheme we choose reference voltages: V1, V2, ... to provide a desired comparison against Vin (these are determined by the specification we are designing for). The comparators provide us a set of binary outputs (I1, I2, ...) which we can decode with digital logic to produce the digital outputs: a1, a2, and a3.
Your lab task is to design, build and tests a 3 bit parallel A/D converter of the general form given in Figure 2. You must design for the specifications given in Table 1. You will use two 339 comparator chips, each having four comparators. Note that the 339 has open collector outputs. In your design process you have several options and choices to make. Analog input voltage may be sent to either the (+) or (-) input of each comparator with the proper reference voltage on the other input. Reference voltages, V1, V2, ..., must be chosen with respect to the specifications given (Table 1). The relatively high input impedances for the 339 comparator help, in easing the design of a network to provide these reference voltages. Try to find a minimal-cost units-realization (total number of gate inputs) for the combinational logic. (I.e: This realization should have no more than four chips.)
Verify that the A/D works. Step the input voltage through various values between 0 and 5 V. Does the output from the A/D change in the manner expected? Use a low-frequency ramp voltage as an analog input and observe the change in the digital output as the ramp varies between zero and five volts.
Include in your test of the A/D’s operation a test for maximum sample rate. Use a square wave input that alternates between 0V and 5V. The maximum sample rate will be the square wave frequency beyond which your comparator outputs (a1, a2, a3) either do not follow the input properly or fail to meet standard TTL voltage output specifications.
Part B. Parallel A/D Converter (Continued)
Table 1. A/D Specifications
Vin - Analog Input Voltage Range (V) / a1 / a2 / a30 - .625 / 0 / 0 / 0
.625 - 1.25 / 0 / 0 / 1
1.25 - 1.875 / 0 / 1 / 0
1.875 - 2.5 / 0 / 1 / 1
2.5 - 3.125 / 1 / 0 / 0
3.125 - 3.75 / 1 / 0 / 1
3.75 - 4.375 / 1 / 1 / 0
4.375 - 5.0 / 1 / 1 / 1