MIPS Core instruction set (subset)
Mnemonic Description Format Except Operation Opcode / Funct (hex)
add Add R (1) R[rd] = R[rs] + R[rt] 0 / 20
addi Add Immediate I (1)(2) R[rt] = R[rs] + SignExtImm 8
addiu Add Immediate Unsigned I (2) R[rt] = R[rs] + SignExImm 9
addu Add Unsigned R R[rd] = R[rs] + R[rt] 0 / 21
and And R R[rd] = R[rs] & R[rt] 0 / 24
andi And Immediate I (3) R[rd] = R[rs] & ZeroExtImm C
beq Branch On Equal I (4) branch if(R[rs] == R[Rt]) 4
bne Branch On Not Equal I (4) branch if(R[rs] != R[Rt]) 5
j or b Jump J (5) PC = JumpAddr 2
jal Jump And Link J (5) $ra = PC+4; PC = JumpAddr 3
jr Jump Register R PC = R[rs] 0 / 08
lbu Load Byte Unsigned I (2) 0 / 24
lhu Load Half Unsigned I (2) 0 / 25
lui Load Upper Immediate I R[rt] = {H16: imm, L16: zeros} F
lw Load Word I (2) R[rt] = M[R[rs]+SignExtImm] 0 / 23
nor Nor R R[rd] = ~ (R[rs] | R[rt] ) 0 / 27
or Or R R[rd] = R[rs] | R[rt] 0 / 25
ori Or Immediate I (3) R[rt] = R[rs] | ZeroExtImm D
slt Set (if) Less Than R R[rd] = (R[rs] < R[rt]) ? 1 : 0 0 / 2A
slti Set Less Than Immed I (2) R[rt] = (R[rs] < SignExtImm) ? 1 : 0 A
sltiu S.L.T Immed Unsigned I (2)(6) R[rt] = (R[rs] < SignExtImm) ? 1 : 0 B
sltu Set Less Than Unsigned R (6) R[rd] = (R[rs] < R[rt]) ? 1 : 0 0 / 2B
sll Shift Left Logical R R[rd] = R[rs] < ShiftAmount 0 / 00
srl Shift Right Logical R R[rd] = R[rs] > ShiftAmount 0 / 02
sb Store Byte I (2) 28
sh Store Half I (2) 29
sw Store Word I (2) M[R[rs] + SignExtImm] = R[rt] 2B
su Subtract R (1) R[rd] = R[rs] - R[rt] 0 / 22
subu Subtract Unsigned R R[rd] = R[rs] + R[rt] 0 / 23
Other Integer Arithmetic Instructions and a Minimal Set for Double
div Divide R Lo = R[rs] / R[rt]; Hi = R[rs] % R[rt] 0 / 1A
divu Divide Unsigned R (6) Lo = R[rs] / R[rt]; Hi = R[rs] % R[rt] 0 / 1B
mfhi Move From Hi R R[rd] = Hi 0 / 10
mflo Move From Lo R R[rd] = Lo 0 / 12
mult Multiply R {Hi,Lo} = R[rs] * R[rt] 0 / 18
multu Multiply Unsigned R (6) {Hi,Lo} = R[rs] * R[rt] 0 / 19
l.d fd, addr cvt.s.d fd, fs #convert double to single
s.d fs, addr cvt.w.s fd, rs #convert single to word
mov.d fd, fs cvt.d.l fd, fs #convert long long floating to double
add.d fd, fs, ft Convert floating (y) to integer (x) with explicit rounding
div.d fd, fs, ft round.x.y rd, fs ex. round.w.s $r6, $f4
mul.d fd, fs, ft trunc.x.y rd, fs
sub.d fd, fs, ft ceil.x.y rd, fs
sqrt.d fd, fs floor.x.y rd, fs
recip.d fd, fs Test and affect condition code c1 (3 from the list of 16)
rsqrt.d fd, fs c.cond.d fs1, fs2 { Where cond can be eq, lt, le and others }
abs.d fd, fs Branch if code c1 is true or false
neg.d fd, fs bc1t label # note that is a one(1), not an ell(L)
bc1f label
Pseudo-Instruction Set
blt Branch Less Than branch if( R[rs] < R[rt] )
bgt Branch Greater Than branch if( R[rs] > R[rt] )
ble Branch Less Than or Equal branch if( R[rs] <= R[rt] )
bge Branch Greater Than or Equal branch if( R[rs] >= R[rt] )
la Load Address R[rt] = R[rs] + ZeroExtImm R[rt] = label R[rs] = label + R[rt]
li Load Immediate R[rd] = immedate
move Move R[rt] = R[rs]
Exceptions (Code: H16 highest order 16 bits, L2: lowest order 2 bits)
(1) May cause overflow Exception
(2) SignExtImm = 16 copies of sign bit [15] + imm16
(3) ZeroExtImm = zeros16 + imm16
(4) BranchAddr = 14 copies of sign bit + addr16 + zeros2
(5) JumpAddr = Copy of top 4 bits of PC + jumpAddr26 + zeros2
(6) Operands considered unsigned (not 2’s complement)
Note: The assembler can generate appropriate translations in situations where a 32 bit address or an immediate longer than 16 bits must be assembled. As a result, many apparent instructions are assembled as groups of pseudo-instructions, and some pseudo-instructions can be assembled several different ways depending upon the addressing modes needed. For example:
lw $t2, label add $t1, 0x12345
sw $t3, label($t4) la $t4, array($s3)
li $t0, 0x12345 beq aLabelTooFar
Assembler directives (subset)
.align .asciiz .byte .data .double .dword .end .ent .extern
.float .globl .half .lab .mask .section .text .word
General Register Assignments Floating Assignments
Name Numbers Use Preserved
$zero 0 The constant value 0 N.A. $f0,$f2 $fv0,$fv1 function return
$at 1 Assembler Temporary No $f4 - $f10 $ft0 - $ft3 temporaries
$v0-$v1 2-3 Function Results No $f12, f14 $fa0,$fa1 function args
$a0-$a3 4-7 Function Arguments No $f16,$f18 $ft4,$ft5 more temps
$t0-$t7 8-15 Temporaries No $f20 - $f30 $fs0 - $fs5 saved regs
$s0-$s7 16-23 Saved Temporaries Yes
$t8-$t9 24-25 Temporaries No
$k0-$k1 26-27 Reserved for O.S. Kernel No
$gp 28 Global Pointer Yes
$sp 29 Stack Pointer Yes
$fp 30 Frame Pointer Yes
$ra 31 Return Address Yes
SPIM Exception Handler Services
Service Code in $v0 Argument Returned Value
Print Integer 1 $a0 == integer
Print Float 2 $f12 == float
Print Double 3 $f12 = double
Print String 4 $a0 == string address
Read Integer 5 $v0 ß integer
Read Float 6 $f0 ß float
Read Double 7 $f0 ß double
Read String 8 $a0 == buffer address (null terminated string is placed in buffer)
$a1 == buffer length
Allocate Memory 9 $a0 == number of bytes $v0 ß address
Exit 10
Basic Instruction Formats (Remember, rd is rightmost here but leftmost in the instruction.)
R opcode6 + rs5 + rt5 + rd5 + shamt5 + funct6 ex. addu $rd, $rs, $rt
I opcode6 + rs5 + rt5 + immediate16 beq $rs, $rt, label ori $rd, $rs, 0xff
J opcode6 + address26 j loop
IEEE 754 Floating Point Single and Double Precision Formats (normalized values only)
All normalized values assume a 1 to the left of the binary point. Only the “fraction” is stored.
Sign1 + Exponent8 + Fraction23 (Exp bias 127) (An exponent all zeros or all ones
Sign1 + Exponent11 + Fraction52 (Exp bias 1023) signals a special value.)