Automatic Generation of Test Pattern for Register Circuit to Achieve 100% Fault Coverage

Automatic generation of test pattern for register circuit to achieve 100% fault coverage

Ye HuangCheng Xiulan

School of microelectronicsSchool of microelectronics

ShanghaiJiaotongUniversityShanghaiJiaotongUniversity

Shanghai, P. R. China 200240Shanghai, P. R. China 200240

Abstract

This paper gives an analysis of the feasibility to achieve 100% fault coverage on register circuit and implements a method to automatically generate test patterns. The target circuit includes the register address decoder and data storage circuit. The s-a-0/s-a-1 fault model was choosed for this research. Through one perl script, the target register information is interactively inputed and the test pattern is outputed. This method is proved to achieve 100% s-a-0/s-a-1 type fault coverage on pure register circuits.

Keywords:test, fault coverage, register, test pattern

1Introduction

Integrated circuit test is becoming more and more important as the industry develops[1]. Test pattern generation and fault coverage are critical points in IC test. In this paper we study on the simplest stuck faults: s-a-0/s-a-1 faults. Achieving 100% fault coverage is practical for some register circuits only include data storage cell and address decoder. In this paper we give an analysis of the feasibility to write this kind of test pattern. In addition, the generation ofthis type of pattern can be done automatically by scripts. We developed our perl script to do this work. And finally we proved our previous analysis with 100% coverage by fault simulation.

2Test preparation

In this chapter, we give the circuit example used through this paper, introduce the fault simulation environment and fault model.

2.1Circuit example

We focus our attention on “pure” register circuits, that is, the circuit only contains data storage circuit and address decoder circuit. In our circuit, the register has 8-bit data bus and 8-bit address bus. An additional 1-bit bank bit is supplied to identify which memory bank the register is at. Our example chip has two banks, bank 0 and bank 1. The register address is defined use (bank number, address) like (0,20h), (1,33h) or (X,6Ch). X in bank number means register exists in both memory bank 0 and 1.

2.2Fault simulation environment

Fault simulation is used to verify the test pattern coverage. We use Syntest Turbofault in our work. The test pattern is text format includes these commands:

(1)`IOW(address, value)

(2)`IOR(address, value)

(3)`ST(text)

In above commands, address is 8-bit register address within a memory bank, and value is an 8-bit binary number. IOW is used to write register, IOR is used to read back and check the register’s content. IOR is the only command to detect faults. Once a fault is activated in a circuit, if this can cause any IOR to generate mismatch (0 becomes 1 or 1 becomes 0), then this fault is hard detected. If the mismatch contains X(0/1 becomes X), then that fault is potentially detected. A fault that is potentially detected by several IOR commands is probably detected. When reporting the final fault coverage, hard detected and probably detected faults will contribute to the coverage. ST is used for tester to know the pattern name.

The test pattern is converted to verilog modules then integrated into the full chip simulation environment to run fault simulation. This part is not covered in this paper.

2.3Fault model

In this paper, we adopted the simplest stuck fault model. That means we only take the s-a-0/s-a-1 faults into account in our study. Bridge faults, temporary faults, delay faults and other kind of faults are not considered for sake of the simplicity.

3Analysis of feasibility to test register circuit

In this chapter, we analyzed the feasibility to get 100% fault coverage in pure register circuits. The circuit will be analyzed in two parts: data storage cell circuit and address decoder circuit.

3.1Data storage cell

3.1.1Circuit analysis

Fig 1: Data storage cell circuit

Fig 1 shows the register’s data storage cell. That is an array of eight parallel storage bits which use 8-bit width data bus (DB<7:0>) to read out and write in data. RESET_ pin is available to reset the data stored in the cell. CS (chip select) pin and READ/WRITE pins(R/S in the picture) are used through AND gates I12,I14 to control the Read/Write of the register. The D flip flop array I11<7:0> in the center is the core element of the storage cell. Data writing is enabled by C pin (CLOCK) which is the output of AND gate I12 with SEL and W as the inputs, data reading is enabled by the output buffer controlled by the output of AND gate I14 with SEL and R as the inputs. For D<7:0>, it is used inside the data storage cell to maintain the data but is unconnected outside.

3.1.2Faults summary

This simple circuit includes these faults to be covered:

(1)S-a-0/s-a-1 faults at C,D,Q pins of the D flip flop array I11<7:0>.

(2)S-a-0/s-a-1 faults at Y,A pins of the inverter I5.

(3)S-a-0/s-a-1 faults at X,A,EN pins of the tri-state gate I13.

(4)S-a-0/s-a-1 faults at A,B,X pins of the two AND gates I12,I14.

3.1.3Test procedure

According to the structure of the circuit, we can give the procedure to test the circuit:

(1)After power on, read and check the initial value of the register(00h) before doing any read/write operation to the register. For the chip design used as an example in this paper, it has POR(power on reset) function, which means after power on, global reset will be activated to reset the value of all the registers. If the faults in inverter I5 make this RESET signal not work, the register’s initial value will be X state. For the fault simulation tool used as an example, an zero value in good machine, if read as x value in fault machine, the corresponding fault is marked as potentially detected (50% probability of fault detection), if we read and check the initial value of the register several times, the fault will be marked as probably detected(75%,87.5%,… probability of fault detection). We use this formula: Optimal coverage=(hard detected faults + probably detected faults)/total number of faults. Finally we can make the detection probability enough high so we can classify the fault as detected.

(2)Write every bit of the register with ONE (for the 8-bit register that is FFh) and then read back and check.

(3)Write every bit of the register with ZERO (for the 8-bit register that is 00h) and then read back and check.

In procedure (2), we have to use another register as the “assistant register”. We now call the register we are testing as “target register”. Before writing FFh to target register, we first write 00h to assistant register and before reading FFh from target register, we first read 00h from assistant register. This method can make sure the data bus is flipped enough to detect the s-a-0/s-a-1 faults at the data bus. Similar method is applied to procedure (3). The read/write operation in procedure (3) can be repeated several times to remove the potentially detected faults.

3.1.4Test pattern

Now we are going to write the test pattern. As in this example, test language use IOR, IOW to stand for IO read/write operation to registers. The test pattern for the register’s data storage circuit is showed below (in this example, the register is in bank 0 and 1, address is (X,6Ch), power on reset value is 00h):

//Read POR value of the register at (X,6Ch) to cover data register reset ports st0 faults.

`IOR(6C,00);

//Register (X,6Ch) read and write test

`IOW(F0,00);

`IOW(6C,FF);

`IOR(F0,00);

`IOR(6C,FF);

`IOW(6C,00);

`IOR(6C,00);

3.1.5Fault simulation

Then we use Syntest Turbofault to run the fault simulation. The result shows the test pattern achieve a 100% fault coverage of the data storage circuit. Fig 2 is a section of the simulation report on data storage cell:

Fig 2: Fault simulation report on data storage cell

3.2Address decoder

3.2.1Circuit analysis

Fig 3: Address decoder circuit

Fig 3 shows the address decoder. DA<7:0> is the global address bus. In our example, the register has 8 bit address. Actually, in our chip as example, this is only address within one memory bank.Our chip has two memory banks, bank 0 and bank 1. The register address is defined use (bank number, address) like (0,20h), (1,33h) or (x,6Ch). Fig 3 is the address decoder for registers (x,6Ch),(x,6Dh),(x,6Eh),(x,6Fh), which means the registers are both accessible in bank 0 and bank 1, and the addresses are from 6Ch to 6Fh.

In the circuit, DA<7:0> is the global address bus, each bit of the bus is decoded to generate the chip select signal (REG<0>,REG<1>,REG<2>,REG<3>) for the four registers whose addresses are (x,6Ch),(x,6Dh),(x,6Eh),(x,6Fh) respectively, as shown in fig 4 below.

Fig 4: Address decoder and data storage cells

3.2.2Faults summary

For this decoder circuit, all the stuck-at faults we should cover locate in the AND gates and NOR gate in left side of Fig 3. A simple way to cover all these s-a-1/s-a-0 faults is “brute force” method.

3.2.3Test procedure

That method is described below (suppose we are test register at (0, F8h)):

(1)Set register bank for target register (bank zero).

(2)Write a value (FFh) into the target register at (0, F8h).

(3)Write a value (00h) which is different from which we used in (2) into 8 registers. Those registers have addresses only one bit different from the target register’s address: (0,78h), (0,B8h), (0,D8h),(0,E8h),(0,F0h),(0,FCh),(0,FAh),(0,F9h).

(4)Switch to another bank (bank one) which is different from procedure (1).

(5)Write a value (00h) which is different from which we used in (2) into register at (1,F8h).

(6)Switch to the bank where target register is located (bank zero).

(7)Read back the target register (0,F8h) and check its value(FFh).

3.2.4Test pattern

Now we are going to write the test pattern. As in this example, test language use IOR, IOW to stand for IO read/write operation to registers. We write register at (X,F7h) to switch bank, the bank bit is the 4th bit from left. The test pattern for the register’s data storage circuit and decoder circuit is showed below (in this example, the register is in bank 0, address is (0,F8h), its power on reset value is 40h):

//Read POR value of the register at (0,F8h) to cover data register reset ports st0 faults.

`IOW(F7,00); //Bank zero

`IOR(F8,40);

//Register (0,F8h) read and write test

`IOW(F7,00); //Bank zero

`IOW(F0,00);

`IOW(F8,FF);

`IOR(F0,00);

`IOR(F8,FF);

`IOW(F8,00);

`IOR(F8,00);

//Register (0,F8h) address decoder test

`IOW(F7,00); //Bank zero

`IOW(F8,FF);

`IOW(78,00);

`IOW(B8,00);

`IOW(D8,00);

`IOW(E8,00);

`IOW(F0,00);

`IOW(FC,00);

`IOW(FA,00);

`IOW(F9,00);

`IOW(F7,10); //Bank one

`IOW(F8,00);

`IOW(F7,00); //Bank zero

`IOR(F8,FF);

3.2.5Fault Simulation

After fault simulation, we can find that the stuck-at faults located in the decoder circuit are all detected. This pattern is aimed at a different circuit not only contains data storage cell and address decoder, so we check the fault coverage result in gate level, the result is not showed here. In chapter 4, an overall result of pure register array circuit will be posted.

3.3Summary

In this chapter, we have concluded that it is feasible to write test pattern achieving 100% fault coverage on pure register circuits.

4Automatic generation of test patterns

We already have proven that it is feasible to write test vector to completely test the register circuit. But manually writing the vector is of course time consuming and not economical, especially for a group of registers under test. So we developed a perl script to handle this work.

4.1Script user guide

This script is a perl script and can be executed in any OS supporting perl environment.When the script is executed, it will interactively ask the user to input parameters in three steps:

1.Pattern name

This name will be used as the file name of the output pattern and used in `ST() command in the first line of the pattern. This command is for tester usage.

For example, if user inputs PFRAME_TMPREGS, the output file name will be PFRAME_TMPREGS.in and the first line of the file will be `ST(PFRAME_TMPREGS). If user enters a blank line in this step, output pattern will use the default name test.in and the first line of that file will be `ST (test).

2.Author name

This parameter will be used to generate comments in output pattern. Blank line as input will leave the author name field blank.

3.Register addresses, POR values and the most-1 value of that register

In this step, the user should input at least one register address and its POR value. The full address includes the bank number (0,1,or x) and address in bank. The most-1 value is the register’s possible with most bits filled with ones.

The register address, POR value and most-1 value should be inputted like one of these formats:

(1)0,f8h,40,FF for all the registers only exists in bank 0.

(2)1,d0h,00,FF for all the registers only exists in bank 0.

(3)x,6ch,00,FF for all the registers exists both in bank 0 and 1.

After entering one valid register address, the user can continue inputting as much registers as he like or press Ctrl+D (in linux environment) or Ctrl+Z(in windows environment) to end the input.This step is case insensitive.

We also have developed another version of this script, the only change is in step 3, we use file as input, which is useful for batch operation. The script using command line input will be a attachment of this paper.

4.2Script usage example

Now we try the script on one module of the example chip which is composed of pure data storage and address decoder. The circuit is just in Fig 3, the four-register array circuit.

We run the script in windows and input the parameters like in Fig 5:

Fig 5: Script usage example

The generated script is showed below.

`ST(test);

//////////////////////////////////////////////////////////////////////////////

//// Author: ////

//////////////////////////////////////////////////////////////////////////////

//Read POR value of the register at (X,6Ch) to cover data register reset ports st0 faults.

`IOR(6C,00);

//Read POR value of the register at (X,6Dh) to cover data register reset ports st0 faults.

`IOR(6D,00);

//Read POR value of the register at (X,6Eh) to cover data register reset ports st0 faults.

`IOR(6E,00);

//Read POR value of the register at (X,6Fh) to cover data register reset ports st0 faults.

`IOR(6F,00);

//Register (X,6Ch) read and write test

`IOW(F0,00);

`IOW(6C,FF);

`IOR(F0,00);

`IOR(6C,FF);

`IOW(6C,00);

`IOR(6C,00);

//Register (X,6Dh) read and write test

`IOW(F0,00);

`IOW(6D,FF);

`IOR(F0,00);

`IOR(6D,FF);

`IOW(6D,00);

`IOR(6D,00);

//Register (X,6Eh) read and write test

`IOW(F0,00);

`IOW(6E,FF);

`IOR(F0,00);

`IOR(6E,FF);

`IOW(6E,00);

`IOR(6E,00);

//Register (X,6Fh) read and write test

`IOW(F0,00);

`IOW(6F,FF);

`IOR(F0,00);

`IOR(6F,FF);

`IOW(6F,00);

`IOR(6F,00);

//Register (X,6Ch) address decoder test

`IOW(6C,FF);

`IOW(EC,00);

`IOW(2C,00);

`IOW(4C,00);

`IOW(7C,00);

`IOW(64,00);

`IOW(68,00);

`IOW(6E,00);

`IOW(6D,00);

`IOR(6C,FF);

//Register (X,6Dh) address decoder test

`IOW(6D,FF);

`IOW(ED,00);

`IOW(2D,00);

`IOW(4D,00);

`IOW(7D,00);

`IOW(65,00);

`IOW(69,00);

`IOW(6F,00);

`IOW(6C,00);

`IOR(6D,FF);

//Register (X,6Eh) address decoder test

`IOW(6E,FF);

`IOW(EE,00);

`IOW(2E,00);

`IOW(4E,00);

`IOW(7E,00);

`IOW(66,00);

`IOW(6A,00);

`IOW(6C,00);

`IOW(6F,00);

`IOR(6E,FF);

//Register (X,6Fh) address decoder test

`IOW(6F,FF);

`IOW(EF,00);

`IOW(2F,00);

`IOW(4F,00);

`IOW(7F,00);

`IOW(67,00);

`IOW(6B,00);

`IOW(6D,00);

`IOW(6E,00);

`IOR(6F,FF);

4.3Fault simulation of example pattern

Run fault simulation use Syntest Turbofault, we get this report:

Fig 6: Fault simulation result on four-register array circuit

Fig 6 shows that we can achieve 100% fault coverage in pure register data storage and address decoder circuit.

5Conclusion

Achieving 100% fault coverage on pure register circuits only contains data storage cells and address decoders are proved to be feasible and the pattern can be generated automatically use perl scripts. This can save a lot of engineers’ manual work and effectively speed up chip test.

References

[1] Michael L. BushnellVishwani D. Agrawal (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Springer.

Appendix

The perl script (command line input):

Regpatgen.pl

The file can be downloaded from

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