MODELLING AND SIMULATION OF SIGMA-DELTA ADC IN VHDL-AMS
Maria Rizzi*, Nicola Rosito^, Beniamino Castagnolo*
* Dipartimento di Elettrotecnica ed Elettronica,
Politecnico di Bari
V. E. Orabona, 4 - 70125 Bari
Italy
^ ST Microelectronics
Agrate, Milano (Italy);
Abstract: Due to the high integration density of the modern electronic circuits, the behavioural modelling is necessary to predict the performace of systems. Adopting different hardware description languages, various levels of abstraction in modelling systems are possible, such as system level, algorithm description, functional blocks and gate-level net list. In this paper, the building blocks of converters are modelled using the VHDL-AMS language and its performance are evaluated
Key words: modulator, VHDL language, design simulation
1. Introduction
The technological improvement in microelectronic field lead to the increase of the integration density and complexity of electronic circuits. An automatic instrument is necessary to simplify the work of designers and to predict the real behaviour of complex circuits.
Being, simulators resources limited both in efficiency and in computing, verification could lead to unacceptable simulation times and algorithm divergences. Therefore, the behavioural modelling has been introduced to design complex systems.
In this paper, the building blocks of converters are modelled using VHDL-AMS language and its usefulness for planning and rearranging design procedure is shown.
2. convertion
A converter consists of integrators and a quantizer (fig.1)
The quantizer is modelled as a simple unfixed K gain block [1] and a summing block into which the quantization noise is injected. In a single bit converter the quantizer is a simple comparator.
The output is a digital signal containing a given fraction of the quantization noise which is out of the band of interest. Since the sampling frequency is much higher than the Nyquist rate, the quantization noise is filtered out by a simple low-pass filter without affecting the informative content of the input signal.
To determine the effect of the quantization noise, a statistical approach has to be used considering the quantization error uncorrelated with the input signal and, therefore, uniformly distributed [2], [3].
The output signal is [4]:
(1)
where STF and NTF are the signal and noise transfer functions respectively having the following expressions:
for (2)
for (3)
In the previous expressions H(z) is the transfer function of a digital integrator, equal to:
(4)
For modulators of order n, the output signal is:
(5)
where E(z) represents the z-transform of the quantization noise. Increasing n, resolution grows but the converter is not stable [1], [3].
An important figure of merit is the dynamic range (DR), defined as the ratio between the maximum applicable signal power and the noise floor which is a measure of the maximum resolution of the converted output signal.
Neglecting non linear effects, DR is expressed as follows [5]:
(6)
where OSR is the ratio between the sampling frequency and the double of the signal band, b is the number of output levels and n is the order of the quantizer.
Performance of typical modulators is measured by different parameters such as power spectral density and dynamic characteristic, which represents a relation between the SNR and the ratio between signal input and reference voltages.
In order to evaluate SNR parameter, the Fast Fourier Transform (FFT) algorithm is used, whose resolution depends on the adopted samples number. In the time domain, the signal is repeated periodically with period mTs where Tsis the sampling period and m is the total number of samples (temporal window).
Adopting the Hanning window (fig.2), the leakage due to the side lobes decreases, but because of the large main lobe, the peak corresponding to the fundamental frequency tends to smear. Most of the power is concentrated in the fundamental and in the adjacent frequency samples.
To choose the samples number, a good trade off between CPU-time and resolution is reached with 216 samples.
3. VHDL-AMS modelling and simulation
Circuit simulation is a fundamental step in the design process of integrated circuits whose components cannot be modified once manufactured. Sometimes, electrical simulations of complex systems may become unfeasible in terms of computational resources and elapsed time. For oversampling converters, performance analysis involves the computation of a large number of samples at the modulator output. This means a very long transient simulation time. In order to reduce the simulation time, behavioural simulations can be performed that lead to reliable results provided that models include contour conditions and sources of error. In the following subsections, the building blocks of - converters are analyzed in VHDL-AMS language. In order to simplify the model, the integrator has been considered as being composed of an amplifier (either operational or transconductance amplifier) and switches (sample-hold section).
- Comparator model
The classical scheme of a comparator is composed of a first stage, able to detect the sign of the differential input signal and a second stage represented by a latch [6].
The VHDL-AMS comparator modelling needs two non-overlapped clock phases as shown in fig.3.
The comparator can switch only on the front edge. For the remaining part of the period, the output voltage is constant.
The arctangent shape is adopted for the static characteristic of the comparator.
Due to the comparator position inside the converter scheme, the impact of comparator non-idealities in modelling the modulator is much lower than that of the integrator. Two important aspects are: the offset voltage and the hysteresis. An offset voltage is attenuated by the DC gain of the integrator. When the converter order is high, the modulator is insensitive to such error. The hysteresis causes a loss of resolution and the comparator switches when the difference signal voltage is higher or lower than the threshold voltage.
- Amplifier model
The amplifier inside the integrator can be realized adopting either an operational amplifier (OPAMP) or a transconductance amplifier (OTA).
In VHDL-AMS the OPAMP is modelled as represented in fig.4 [7].
The model can be detailed according to the parameters that need to be considered, such as the dominant pole, the first non-dominant pole, the finite differential gain and the common mode gain. Modelling the second stage with a voltage controlled current source in parallel with a resistor and a capacitor, and limiting the current to a maximum value, it is possible to study the influence of the slew rate. Amplifier gain, input parasitic capacitances, output impedances and finite slew rate are also taken into account.
The structure of OTA is indicated in fig.5.
As low output current allows us to reduce the power consumption, the OTA is the adopted amplifier for this type of converter. The schematic of OTA is a simple stage fully differential folded cascode.
- Switch capacitor model.
Adopting the VHDL-AMS language, some parts of mixed circuits can be implemented at transistor level. Due to the presence of a large number of transistors, the simulation time is long.
As it is possible to implement equations including discontinuity, the mathematical model for sample and hold circuits can also be found.
In fig. 6 the model of the switch is presented. The switch is modelled adopting a low or high value resistance, according to the switch state. The model takes into account the different paths of discharge of sampling capacitors during the integration phase.
4. Performance evaluation
Different simulations were performed using both OTA and OPAMP amplifiers and the obtained performance is evaluated considering the accuracy of results and flexibility of models.
The dynamic characteristic of the converter implemented with OTA is plotted in fig.7.
The mean error and the standard deviation of the SNR differences are approximately 0.3dB and 2.7dB respectively.
Adopting the OPAMP model, the simulation gives the same value for the previous two parameters.
VHDL-AMS models simplify analysis of the influence of parameter variations.
One of the most important parameters is the differential gain of the amplifier which validates (or not) the use of an ideal model for the OPAMP. In order to evaluate the contribution of the differential gain, the SNR versus the gain has to be plotted (fig.8).
Using the folded cascode structure for the OTA amplifier, the pole depends on the output load; low frequency poles slow down the amplifier and this will not be able to follow the signal variations. The SNR parameter has been computed for different pole frequencies (fig.9) considering a maximum signal amplitude of – 4dB so as to avoid the overload phenomenon.
Poles having a frequency higher than 10KHz have no influence.
- Conclusions
The high integration density of VLSI technology makes necessary a fast estimation of system performance. The VHDL-AMS language makes this possible as it permits flexibility in the selection of topology, architectural level simulation and the simulation of the non idealities of the building blocks of the whole structure.
The design criteria of a - converter have been examined using VHDL-AMS. The simulation of converter behaviour is possible even if a longer simulation time is necessary in comparison with other tools such as Matlab.
Post-layout measures of the converter parameters were in accordance with the modelled results.
References
[1] R. T. Baird, T. S. Fiez: Stability analysis of High-OrderDelta-Sigma Modulation for ADC’s, IEEE Transactions on Circuits and Systems-II, 41(1), 1994 ,59-62.
[2] F. Maloberti, P. Jonnaeum: Analog-Digital ASICS’, 149-151,159-161.
[3] T. Ritoniemi, T. Karema, H.Tenhunen: Design of a stable High-Order 1-Bit Sigma-Delta Modulators, Tampere, University of Technology, Finland; IEEE 1990 pp. 3267-3268.
[4] F. Medeiro, A. P. Verdu’, A. Rodriguez-Vazquez: Top-Down-Design of High Performances Sigma-Delta Modulators, (Kluiver Academic Publishers, Boston 1999), cap.2-3.
[5] V. Peluso, M. Steyaert, W. Sansen, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters, (Kluiver Academic Publishers, Boston 1999), 9-12.
[6] F. Wang, R. Harjani: Design of Modulators for Oversampled Converters’ (Kluever Academic Publishers, Boston 1998), 124-130.
[7] M. Vogels, B. De Smedt, G. Gielen: Modeling and Simulation of a Sigma-Delta Digital to Analog Converter using VHDL-AMS’ 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, October 18-20/2000 Orlando (Florida).
Fig.1: High order converter
Fig. 2: Hanning window.
Fig. 3: Clock phases
Fig. 4: Operational amplifier model.
Fig. 5: Amplifier in transconductance model.
Fig. 6 Switches model during sampling (a) and integration phase (b).
Fig. 7: Dynamic characteristic of the converter implemented with OTA.
Fig. 8: SNR versus differential gain variations
Fig. 9: SNR versus pole variations.
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