3D1-Microprocessor Systems 1

Lecture 26: Introduction to the System Bus –Data Transfer Operations

After introducing the processor’s control I/O signals we now describe thesignal and bus operation for some 16-bit data transfer operations including Read/Write cycle and interrupt acknowledge cycle.

Learning Outcomes:

On completion of this lecture, you will be able to:

  • Describe the sequence of events in a Read/Write cycle;
  • Describe Read/Write timing diagrams;
  • Identify the processor signals involved in an interrupt acknowledgment cycle;
  • Distinguish between vectored and non-vector interrupt acknowledge.

26.1 Read Cycle

During a read cycle, the processor receives either one or two bytes of data from thememory or from a peripheral device. If the instruction specifies a word or long-wordoperation, the processor reads both upper and lower bytes simultaneously by asserting both upper andlower data strobes. When the instruction specifies byte operation, the processor uses theinternal A0 bit to determine which byte to read and issues the appropriate data strobe:

  • when A0 equals zero, the upper data strobe is issued;
  • when A0 equals one, the lowerdata strobe is issued.

When the data is received, the processor internally positions thebyte appropriately.The read-cycle flowchart and timing diagrams are shown in Figure 29.1 and 29.2 respectively.

Fig.26.1: Word Read-Cycle Flowchart

A bus cycle consists of eight states. The various signals are asserted during specificstates of a read cycle, as follows:

  • STATE 0 The read cycle starts in state 0 (S0). The processor places valid functioncodes on FC0–FC2 and drives R/W’high to identify a read cycle.
  • STATE 1 Entering state 1 (S1), the processor drives a valid address on the addressbus.
  • STATE 2 On the rising edge of state 2 (S2), the processor asserts AS and UDS, LDS, or DS.
  • STATE 3 During state 3 (S3), no bus signals are altered.
  • STATE 4 During state 4 (S4), the processor waits for a cycle termination signal(DTACK or BERR) or VPA, an M6800 peripheral signal. When VPA is asserted during S4, the cycle becomes a peripheral cycle. If neither termination signal isasserted before the falling edge at the end of S4, the processor inserts waitstates (full clock cycles) until either DTACK or BERR is asserted.
  • STATE 5 During state 5 (S5), no bus signals are altered.
  • STATE 6 During state 6 (S6), data from the device is driven onto the data bus.
  • STATE 7 On the falling edge of the clock entering state 7 (S7), the processor latchesdata from the addressed device and negates AS, UDS, and LDS. Atthe rising edge of S7, the processor places the address bus in the highimpedancestate. The device negates DTACK or BERR at this time.

NOTE: During an active bus cycle, VPA and BERR are sampled onevery falling edge of the clock beginning with S4, and data islatched on the falling edge of S6 during a read cycle. The buscycle terminates in S7, except when BERR is asserted in theabsence of DTACK. In that case, the bus cycle terminates oneclock cycle later in S9.

Fig.26.2: Read and Write -Cycle Timing Diagrams

26.2 Write Cycle

During a write cycle, the processor sends bytes of data to the memory or peripheraldevice. If the instruction specifies a word operation, the processor issues both UDS andLDS and writes both bytes. When the instruction specifies a byte operation, the processoruses the internal A0 bit to determine which byte to write and issues the appropriate datastrobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS isasserted.The word write-cycle timing diagrams and flowchart are shown in Figure 29.2 and 29.3 respectively.

Figure 26.3: Word Write-Cycle Flowchart

The descriptions of the eight states of a write cycle are as follows:

  • STATE 0 The write cycle starts in S0. The processor places valid function codes onFC2–FC0 and drives R/W high (if a preceding write cycle has left R/W low).
  • STATE 1 Entering S1, the processor drives a valid address on the address bus.
  • STATE 2 On the rising edge of S2, the processor asserts AS and drives R/W low.
  • STATE 3 During S3, the data bus is driven out of the high-impedance state as thedata to be written is placed on the bus.
  • STATE 4 At the rising edge of S4, the processor asserts UDS, or LDS. Theprocessor waits for a cycle termination signal (DTACK or BERR) or VPA, anM6800 peripheral signal. When VPA is asserted during S4, the cyclebecomes a peripheral cycle. If neither termination signal is asserted before the fallingedge at the end of S4, the processor inserts wait states (full clock cycles)until either DTACK or BERR is asserted.
  • STATE 5 During S5, no bus signals are altered.
  • STATE 6 During S6, no bus signals are altered.
  • STATE 7 On the falling edge of the clock entering S7, the processor negates AS,UDS, or LDS. As the clock rises at the end of S7, the processor placesthe address and data buses in the high-impedance state, and drives R/Whigh. The device negates DTACK or BERR at this time.

26.3 Interrupt Acknowledgement Cycle

An interrupt acknowledge cycle places the level of the interrupt being acknowledged onaddress bits A3–A1 and drives all other address lines high. The interrupt acknowledgecycle reads a vector number when the interrupting device places a vector number on thedata bus and asserts DTACK to acknowledge the cycle. The timing diagrams for an interrupt acknowledge cycle is shown in Figure 29.4.Alternately, the interrupt acknowledge cycle can be autovectored. The interruptacknowledge cycle is the same, except the interrupting device asserts VPA instead ofDTACK. For an autovectored interrupt, the vector number used is $18 plus the interruptlevel. This is generated internally by the microprocessor when VPA (or AVEC) is assertedon an interrupt acknowledge cycle. DTACK and VPA (AVEC) should never besimultaneously asserted.

Figure 26.4: Interrupt acknowledgement Cycle Timing Diagram

26.4Conclusion

Transfer of data between devices involves the following signals:Address bus A1 through highest numbered address line, Data bus D0 through D15 and Control signals. The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cases, the bus master must deskew all signals it issues at both the start and end of a bus cycle. In addition, the bus master must deskew the acknowledge and data signals from the slave device.

What happens with an unimplemented address? i.e. the bus master attempts to read/write from/to an addressthat isn’t used by any slave (thus, no slave responds): we need some extra hardware, typically a simple timer, to timeout if a cycle goes on too long. If the timer times out, it signals aproblem by asserting BERR’.

REFERENCES:

  • Signal Description, In: M68000 8-/16-/32-Bit Microprocessors User’s Manual; Section 5;Motorola inc.; 9th ed.; 1993.
  • Dr. Mike Brady, Microprocessor Systems 1, dept of Computer Science, Trinity College Dublin:
  • Look on the Web. Look at

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