MODELING, CHARACTERIZATION AND DESIGN OF WIDE BANDGAP MOSFETS AND MISFETS FOR HIGH TEMPERATURE/HIGH POWER APPLICATIONS

Submitted To: The ARL PEER (Power and Energy Electronics Research) Program

Principal Investigator: University of Maryland(UMD):

Neil Goldsman(Faculty)

Steve Powell(Ph.D. Student), Gary Pennington(Ph.D. Student), Gabriel Lopez (MERIT)

ECE Dept. University of Maryland, College Park, MD20742, 301-405-3648,

Army Research Laboratory Collaborators:

Charles (Skip) Scozzie

Aivars Lelis (ARL & UMD Ph.D Student), Bruce Geil (ARL & UMD M.S. Student)

Background

We propose to investigate the design of new high-temperature/high-power electronics based on silicon carbide (SiC), a material which shows great promise for use in power electronics.

The ARL is designing power-conversion/motor-control systems which can operate at high power densities and high temperatures. To control these systems, we are investigating the design and development of high temperature voltage-controlled electronics. As was demonstrated in industry for room-temperature applications, the optimal component for electronic control circuits was the silicon MOSFET. For high temperature we intend to build on this strategy by developing SiC MOSFETs. SiC is unique in the sense that it appears to be the only semiconductor capable of operating at high temperatures, which can also be used as a basis for MOSFET fabrication.

The relatively recent commercial availability of SiC wafers has significantly increased the possibility of electronics based on SiC MOS technology. Silicon dioxide (SiO2) can now be grown on SiC, thus enabling the fabrication of SiC MOSFETs. By analogy with Si MOSFETs, the realization of SiC MOSFETs provides the potential for extending the electronic revolution to high power and high temperature applications. However, before SiC can be routinely used in electronics, various obstacles must be overcome. As was the case with Si, early SiC MOSFETs have SiO2 interfaces that are subject to high interface trap density, which usually degrades device performance. Interface traps can also be generated during device operation, which may give rise to unstable current-voltage characteristics. Other phenomena affecting SiC MOSFET performance include surface phonon scattering, surface roughness scattering and incomplete dopant ionization. To develop robust SiC MOSFETs, these phenomena must be understood andquantified.

Our research groups at ARL and UMD have established a strong collaboration in a combined experimental-theoretical investigation to understand and quantify phenomena affecting SiC MOSFET performance. Measurements of interface traps and surface mobility were performed at ARL. At UMD, computer-based simulation tools were developed to help understand the results of these experiments, and to design new SiC devices. We have developed a custom drift-diffusion numerical simulator to accurately model physical conditions within SiC MOSFETs.

We also developed a Monte Carlo (MC) simulator for electron transport in the bulk as well as the surface channel in SiC . Key results from our investigations of 6H-SiC devices are[1-6]:

  1. Interface traps are the dominant mechanism degrading mobility at room temperature
  2. Reducing interface traps to Si-like levels will yield a five-fold increase in output currents.
  3. Increasing temperature reduces interface trapped charge, giving rise to improved channel mobility, which results in increased current.
  4. Surface roughness appears to be less important than interface traps in limiting performance.
  5. Surface phonons will dominate performance in devices with Si-like levels of interface traps.

Approach

Having established a foundation, where we have developed specially tailored SiC software, obtained a variety of new experimental devices, and identified key mechanisms governing SiC MOSFET operation, we are ideally situated to perform investigations which can help give rise to high-peformance SiC MOSFETs. To this end, we plan to extend our investigation of 6H-SiC, for high temperature, low voltage control circuits, to include the other promising material polytype, 4H-SiC, which appears promising for high-voltage, high-power, high-temperature device applications. In addition, having identified interface traps as the key mechanism responsible for reduce surface mobility in SiC MOSFFETs, we plan to investigate the fundamental physics underlying the occupation and generation of interface traps and oxide charge, especially that which occurs during device operation.

To investigate the 4H-SiC polytype and the details of interface trap physics we will pursue the following approach. We will perform measurement of SiC MOS and MIS capacitors, MISFETs, and MOSFETs at ARL. Our new devices will be characterized using CV, GV, I-V, and charge pumping techniques for interface, fixed, and trapped-charge densities, and how they depend on temperature and stressing. By working closely with the UMD computer modeling effort, details of the oxide and interface structure will be deciphered (fast states, slow states, energy spectrum, etc.). Using software that we have developed, we will determine the precise physical environment which exists at the interface during device operation and stressing. The drift-diffusion simulator will help to provide the electrostatic potential, carrier concentration and trap concentration at any point along the interface, before and after stressing. We plan to then couple this information into our SiC Monte Carlo simulator, which gives the quantum states of the electrons at the interface. By correlating the electron energy states with trap generation, we expect to develop an atomic model which predicts interface-trap generation. This information will then be used to suggest methods for reducing interface trap generation, and the development of more stable 6H-SiC and 4H-SiC MOSFETs.

Technical Barriers

Many technical barriers must be overcome before SiC MOSFETS can be used in circuits. While Cree Inc. (the leader in SiC materials and devices) has produced SiC MOSFETs, these devices’ performance are far from optimal. The problems to be surmounted include low surface mobility, high interface-trap concentrations, high fixed-oxide charge, relatively low oxide and insulator breakdown fields, and material defects.

In addition to technical barriers associated with the development of SiC MOSFETs, we must overcome barriers to develop our research tools. The drift-diffusion simulator solved a very complex system of nonlinear differential equations. This system becomes increasingly complex as more and more realistic physics is incorporated into the model. Our challenges are to develop a realistic model, and then to develop the numerical algorithms which can solve the mathematical model, and do so efficiently.

Impact of Proposed Research

A new comprehensive, physical model and simulator which significantly enhances design capabilities SiC MOSFET based electronics will be available. The new model can be used for designing SiC MOSFETs to operate over a wide temperature range (-55 to 300C). With the simulator we will be able to probe inside the device, where experimental measurements cannot be taken, and determine the roots of the performance degradation of SiC MOSFETs under the required operating conditions. Once these causes are identified, steps can be taken to modify either the fabrication techniques or the devices’ designs.

Statement of work:

  1. Extend the 2D Drift Diffusion Model to the 4H Polytype SiC MOSFETS. Verify the predictions by comparison with experimental results from ARL.
  1. Extend the Monte Carlo electron transport calculations to make predictions of the temperature dependence on mobility in the 4H SiC Polytype devices. Use these results as input to 2D Model.

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  1. Use the model and the Monte Carlo electron transport calculations to clarify the role played by each of the scattering mechanisms degrading the channel mobility. Investigate the dominant mechanisms as a function of temperature.
  1. Understand the physical mechanisms and device design features that contribute to the degradation of device performance under time, temperature, and bias stress. By fitting the model to the post stress results we hope to enhance our understanding of the causes of the degradation, including the generation of interface traps during operation. (This task should support ARL in its evaluation role in the DARPA program.)
  1. Use device physics results to develop SiC MOSFET SPICE circuit models, and begin designing high temperature control circuits for Army applications using the best state-of-the-art (SOA) material and device characteristics.

Quarterly Milestones/Deliverables:

Q1: Modify the 2D Drift Diffusion model to apply to 4H SiC MOSFETS. Extend the Monte Carlo electron transport calculations to the 4H SiC polytype.

Q2: Verify the 2D Model predictions by comparison with ARL experimental results on 4H SiC MOSFETS as a function of temperature.

Q3: Apply the 2D Model to the investigation and identification of the causes of instabilities and device degradation in 4H and 6H SiC devices.

Q4: Perform a preliminary design of SiC MOSFETS for an ARL high temperature low power logic circuit for control of high temperature power conditioning circuits.

  1. G. Pennington, et al., Proc. International Semiconductor Device Research Symposium, 2001.

2.

  1. G. Pennington, and N. Goldsman, Phy. Rev. B, vol 64, pp. 45104-45108, 2001.
  1. S.K. Powell, et al.,, Proc. International Semiconductor Device Research Symposium. 2001.
  2. S.K. Powell, et al., Journal of Applied Physics, V92, No.6, Sept. 2002.
  3. G. Pennington, et al., 33rd IEEE Semiconductor Interface Specialists Conference, Dec. 2002 (Submitted).
  4. S.K. Powell, et al., 33rd IEEE Semiconductor Interface Specialists Conference, Dec. 2002 (Submitted).

BUDGET

Staffing:

Completing our objectives will require the full time efforts of two UMD graduate students, the part-time effort of one UMD faculty member, as well as the work of ARL scientists. One student will be responsible for Drift-Diffusion type simulations and assistance to the ARL experimental effort. The other student will be involved in Monte Carlo type modeling and analysis at the detailed quantum atomic level. The UMD faculty member will work on model development, provide overall direction, and maintain close collaboration with ARL.

2 Graduate Research Assistants (GRA), 35K each,70K

1 Faculty Support 10K

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Total 80K

1)G. Pennington, and N. Goldsman, "Empirical Pseudopotential Band Structure of 3C, 4H, and 6H SiC Using Transferable Semiempirical Si and C Model Potentials,” Phy. Rev. B, vol 64, pp. 45104, 2001.

2)G. Pennington, N. Goldsman, C. Scozzie, J. McGarrit, F.B. Mclean., “Investigation of Temperature Effects on Electron Transport in SiC using Unique Full Band Monte Carlo Simulation,” International Semiconductor Device Research Symposium Proceedings, pp. 531-534, 2001.

3)S. Powell, N. Goldsman, C. Scozzie, A. Lelis, J. McGarrity, “Self-Consistent Surface Mobility and Interface Charge Modeling in Conjunction with Experiment of 6H-SiC MOSFETs,” International Semiconductor Device Research Symposium Proceedings, pp. 572-574, 2001.

4)S. Powell, N. Goldsman, J. McGarrity, J. Bernstein, C. Scozzie, A. Lelis, “Characterization and Physics-Based Modeling of 6H-SiC MOSFETs”’ Journal ofApplied Physics, V.92, N.7, pp 4053-4061, 2002

5)S Powell, N. Goldsman, J. McGarrity, A. Lelis, C. Scozzie, F.B McLean., “Interface Effects on Channel Mobility in SiC MOSFETs,” Semiconductor Interface Specialists Conference, 2002

6)G. Pennington, S. Powell, N. Goldsman, J.McGarrity, A. Lelis, C.Scozzie., “Degradation of Inversion Layer Mobility in 6H-SiC by Interface Charge,” Semiconductor Interface Specialists Conference, 2002.

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