Programmable Gm-C Equalizer for DVD RF Front-End
Ching-Cheng Tien(田慶誠)1 and Shu-Chuan Yang(楊淑娟)2
1Department of Communication Engineering, ChungHuaUniversity
No. 707, Sec. 2, Wufu Rd., Hsinchu, 30012, Taiwan, R.O.C.
Tel: 03-518-6398 Fax: 03-518-6031
Email:
2 Department of Electrical Engineering, ChungHuaUniversity
No. 707, Sec. 2, Wufu Rd., Hsinchu, 30012, Taiwan, R.O.C.
Tel: 03-518-6391 Fax: 03-518-6436
Email:
Abstract
A full CMOS seventh-order Elliptic filter based on Gm-C biquads with a -3dB tuning frequency of 10MHz to 28MHz is realized in TSMC0.18µm CMOS process.The linear operation transconductance amplifier is base on source degenerated in order to achieve high linearity and high-frequency operation.The common-mode feedback(CMFB) circuit used to stabilize the bias of the filter architecture and a very simple automatic tuning system corrects the filter gm deviations from process parameter tolerances and temperature variation. The supply voltages used are 3.3V. The total harmonic distortion is less than -45.44dB for input signals up to 100mVpp.The filter chip area is only .
Keyword:low pass filter, Gm-C
1.Introduction
Because of the advanced digital and information technology, we not only apply RF front-end circuit to the high frequency communication but also utilize this circuit as parts of the transferring process from digital to analogy information. Though products of high-speed information transfer system, like Cable modem, XDSL, Ethernet, CD/DVD Rom. LVDs series bus, do not deliver its high frequency electromagnetism carrier via air, their reception of analogue fundamental bandwidth could speed up to hundreds MHz or even GHz via the SATA storage interface.
However, all RF front-end circuits require carried or low pass filters, which mainly eliminate high frequency noises and interfering signals above the fundamental. Later on, fundamental analogue signals are sent to ADC and then transformed them to digital signals, applying the process of modifying and outputting signals to digital information. Therefore, we focus on the sub-circuit in RF front-end or the design of the programmable baseband filter, CMOS Equalizer filter in our research.
2. Basic Equalizer Structure
2.1 Principle of Design and Its Approaches
At first, it is necessary to know the specification of the reception system[2], and then try to define the standard of its own. Following the defined standard, an appropriate “transfer function” is conducted in the simulation process of Matlab and Pspice. To function the circuit, I facilitate the active parts to complete the design of filter. If the Active filter does not fit in the defined standard, it is needed to go back to the stage of “filter type” and then to repeat its previous steps.
2.2Equalizer Structure
(1) OTA Circuit
This circuit is aimed to achieve the active filter in a simple design and small measure. Basically, we apply Gm-C Filter as the design of OTA circuit.The filter,utilizingOTA as the equalizer resistance, isconcerned with the linearity of OTA in this design. Sowe strengthen the linearity of OTA by source degenerated.The following is the introduction of OTA circuit (Figure 2-1).
Figure2-1 OTA Circuit
The Figure 2-1 presents the design ofOTAin this thesis. TheM5~M8is the active load that increases the output impedance. Mr1andMr2, is the current source, which modify the value of Gm by changing magnitude ofVT are regarded as the degenerated resistance. M3and M4 are input of this circuit, while is used T-model of MOS to draw a small signal. Figure 2-2.
Figure2-2 OTA small signal Model
The formula of Gm value can be inferred like[6]:
For M3and M4 works in the saturation region
For Mr1and Mr2 operates in the triode region
,
(2-1)
The formula 2-1 tells that the magnitude of Gm follows up with the tuning of voltage VT and forms its linear development. In the Figure 2-1, when VT is fixed (if the channel length modulation was not concerned), the current flow through M1 and M2 will be the same. So, ISS will be also staying the same. From this formula 2-1, the magnitude of Gm has nothing to do with the input signal. For the concern of the relationship between Gm and VT, this formula 2-1 further indicates that Gm is direct ratio to. Therefore, the formula of the saturation transistor current presents Gm is direct ratio to M1、M2,so that Gm is direct ratio to VT. As mentioned above, Gm is direct ratio to VT. Along with the tuning of voltage VT, the linear development takes shape and infers to:
(2-2)
(2-3)
(2) Bias Circuit
Figure2-3 Conventional bias circuit
Figure 2-4 Wide Amplitude Bias Circuit
The Figure 2-3 is the conventional bias circuit whose disadvantage restrain the amplitude. Toincrease the output range, the bias circuit is applied like theFigure 2-4 and further operates one voltage of Vth, compared to the performance of the bias.[7][8][16]
(3) Common Mode Feedback Circuit
The “fully differential” way requires the common mode feedback circuit[9], which consists of two modes: direct and alternate current circuit.This thesis applies the alternate common mode feedback circuit. On the one hand, its advantage is that the circuit is not necessarily manipulated by the additional CLOCK and further reduces the interference of digital signals. On the other hand, the disadvantage of the circuit limits the range of output. In the design of active filter, the range of linearity is the main concern. Without a sufficient performance of the linearity range, the design won’t work successfully even with a wide range of output.When Vicm=(VOP+VON)/2, the Figure 2-5 tells that VCM will stay at the same level. Moreover, when Vicm > (VOP+VON)/2, the increasing current of MC4 and MC5 makes the voltage VCM goes down. From the OTA Circuit, that leads the M7 -M8current to rise up. For VT is fixed, the current of M1and M2 stayed likewise. This further generates the M5 and M6 the channel length modulation(early effect). At the same time, it imitates the arising DC level of VON and VOP to the state of Vicm=(VOP+VON)/2.
Figure2-5 Common Mode Feedback Circuit
(4) The realization of Active Filter
The Figure 2-6 shows the OTA equalizer resistance structure, including the grounded and floating resistance.
Grounded Resistance:
Floating Resistance:
Figure2-6 Grounded and Floating Resistance
(5) The Tuning Circuit
The disadvantage of thealternate Active filter, that is, tends to the tuning circuit. The SC [1]filter with the conduct of CLOCK doesnot require the additional tuning of circuit but adjust with CLOCK.For being short of external reference, Gm-C filterwill cause deviation from the processvariation.Usually tuning the circuit to PLL that makes the circuit complicate, so the voltage comparison as the auto tuning circuitFigure 2-7 would be the solution.[4][5][10][15].
Figure2-7Auto Tuning Circuit Structure
The principle of tuning is based on the voltage comparison. From the Figure 2-1, the Gm value of the sub-circuit design will go up along with VT. The F circuit structure in the Figure 2-8 presents that the voltage comparison of Vref and VF2 =(1/Gm)*Iauto, in the end, brings out the effect of tuning circuit. In other words, tuning the Gm value of OTA with VT. leads to the performance of Vref= VF2.
Figure2-8Tuning Circuit
(6) Gain Boost
The Figure 2-9 shows the Gain boost circuit[2], whichis the filter with the higher frequency gain boostingmechanism.This tuning mechanism of the photo detector compensates the less outputswing (DVD:6-10dB @ Fc) of high frequency signals that is short for the reception time of light reflection. In this circuit, Vggenerates the voltage from the power supply. With varied frequency, the value of voltage will be obtained to reach to its corresponding gain value, further compensating the photo detector’sreception time of light reflection.
Figure2-9 Gain boost Circuit
Figure 3-1 Active Filter Circuit
3. Simulation Results
The filter circuit adopts the OTA design,including four levels of the seventh order differential low pass filter. The Figure 3-1 is the full structure of the active filter circuit[2] in which Gm is composed of theOTAcircuit shown in the Figure 3-2. This circuit presents that Gm1=Gm3and generates differentGmvalue, such as Gm21, Gm22, and Gm23 in each level.
Figure3-2 Full OTA Circuit
When all Gm simulate in different bands, the process of simulation brings out the gain value of frequency response and the high & low of Group delay.
AV / Av(dB) / Group delay(sec)10M
100k~30M / AL =-1.164852 / GL=38.54977n
AH =8.874459 / GH=47.45013n
15M
150k~45M / AL =-1.198537 / GL =30.08364n
AH =8.10942 / GH=38.58398n
20M
200k~60M / AL =-1.233629 / GL=25.3867n
AH =7.49607 / GH =33.53867n
28M
280k~84M / AL =-1.424348 / GL=17.87808n
AH =5.715423 / GH=25.13413n
Ideally, the more gain value is obtained, the better the performance presents. In other word, the less Group delay is carefully measured, the better the outcome exhibits. For mutual influence, it is necessary and inevitable to run a tradeoff between the gain value and the Group delay in the process of simulation.
3.1Frequency Response
The Figure 3-3 presents the frequency response, which has not yet proceeded the Auto tuning. Concerned with the process variation, this result is conducted with the tuning circuit. From the simulation, it is acknowledged that the tuning circuit successfully works in the performance of tuning.
Figure3-3Frequency Response with un-Auto tuning
Figure3-4Frequency Response with Auto tuning
WhenGm1=Gm3, the Gm2of eachlevel differentiates. At the same time, for the measure of the area, it is strongly suggested to select much more Gm1 for Auto tuning circuit. That further leads to a certain error for the Gm2 in each level. However, these errors eventually could be resolved with the DAC fine tuning in the process of measurement.
3.2 Temperature and Frequency Response
From the perspective of various frequencies, that is, (the apex of gain boost circuit) is obviously to show the consequence of Av to the influence of the temperature. Targeting the range between -20 to 100 degree, the influence of changing temperature is controlled within the performance of tuning circuit. However, the result is not so perfect as the tuning of the process variation. This conducted design (or the tuning circuit) could function its fine tuning of the external DAC within in order to meet the required specification.
Av-temp / FC=10M / FC=15M / FC=20M / FC=28M-20 OC / 9.063507 / 8.341864 / 7.798249 / 6.037185
0 OC / 8.9773 / 8.237107 / 7.660568 / 5.876894
20OC / 8.876181 / 8.111677 / 7.495547 / 5.715559
40 OC / 8.76078 / 7.970493 / 7.313299 / 5.549116
60 OC / 8.631122 / 7.813892 / 7.113123 / 5.378591
80 OC / 8.492538 / 7.644135 / 6.902066 / 5.203775
100 OC / 8.340897 / 7.463979 / 6.686237 / 5.024772
3.3Resistance Varied Ratio and Frequency Response
Considering the influence of the resistance varied ratio, the frequency response is processed and sampled as particularly 10% varied ratio of the resistance to observe its influence under different conditions of frequencies.
AV-R10% / Av(dB) / Group delay(sec)10M
100k~30M / AL=-1.179364 / GL=39.06651n
AH=8.825294 / GH =48.710313n
15M
150k~45M / AL=-1.205227 / GL =30.38328n
AH=7.989292 / GH =39.52977n
20M
200k~60M / AL=-1.241751 / GL=25.5625n
AH=7.311552 / GH =34.31498n
28M
280k~84M / AL=-1.432279 / GL=17.98194n
AH=5.453477 / GH =25.64596n
3.4Filter Linearity Analysis (Result of THD Simulation)
In the following, the analysis of FFT focuses on respectively the 10MHz, 15MHz, 20MHz, and 28 MHzsine waves. Changing the amplitude of each level in the simulation brings out the result. Likewise, the error derived from the process variation isconsiderately put into this procedure of simulation.
FC / Fin / TT(dB) / FF(dB) / SS(dB)10M / -31.12086 / -41.12154 / -30.45878
10M
15M12M
15M / -42.95798 / -39.34436 / -39.34436
-47.30563 / -34.6838 / -42.63601
-51.03029 / -31.86816 / -44.94027
10M
20M15M
20M / -44.78687 / -39.06443 / -42.51176
-44.26945 / -31.18474 / -51.62519
-49.98771 / -34.71428 / -56.14399
10M
28M19M
28M / -43.94123 / -39.71828 / -48.79327
-39.75799 / -31.29452 / -64.3825
-45.44489 / -37.93419 / -68.61548
4. Conclusions
The performance summary of proposed equalizer circuit are shown as followed.These simulation results fully satisfy the specifications of DVD RF front-end standards.
Technology / 0.18µm TSMCTuning range(3dB) / 10MHz~28MHz
OTA gm value / 28.2u ~234.3u
Input voltage-AC / 0.1Vpp, max
THD(@15MHz:100mV) / -31dB, max
THD(@20MHz:100mV) / -31dB, max
THD(@28MHz:100mV) / -31dB, max
Group delay / 10ns, max
Power supply / 3.3v
Power consumption(@fc=28M) / 19.99769 mW
Chip size / 928µm x819.001µm
Acknowledgements
The authors would like to thank National Chip Implementation Center(CIC) for technical supports.
References
[1]Un-Ku Moon, “CMOS high-frequency switched-capacitor filter for telecommunication applications,” IEEE J. Solid-State Circuits, Vol. 35, No. 2, pp. 212-220, Feb. 2000.
[2]吳文琦博士,” CD/DVD的類比前級電路”,自強基金會,工研院光電所.
[3] Rolf Schaumann and Mac E. Van Valkenburg, “Design of Analog Filters”,2001.
[4]Shinichi Horiand Tadashi Maeda, “A Widely Tunable CMOS Gm-C Filter With A Negative Source Degeneration Resistor Transconductor”, IEEE, 2003
[5] 陳鈺民, “適用於IEEE802.11a之通道選擇濾波器”,中華大學電機所,Jul. 2003.
[6] David A. Johns and Ken Martin, “Analog Integrated Circuit Design “, 1997
[7]Behzad Razavi, “Design of Analog CMOS Integrated Circuit”,Jul. 2002.
[8]R. Jacob BakerandHarry W. Liand David E. Boyce, “CMOS Circuit Design, Layout, And Simulation” , 1997.
[9]R.J.BAKER, "CMOS Circuit Design, Layout, and Simulation 2/e", 2005.
[10]Francois Krummenacher and Norbert Joehl, “A 4-MHz CMOS Continuous Time With On-Chip Automatic Tuning”, IEEE Journal of Solid-State Circuits, Vol.23, No 3, June 1988.
[11]Worapishet,A.and Naphaphan, C.; “Current-feedback source-degenerated CMOS transconductor with very high linearity”, Electronics Letters,Volume: 39,Issue:1,9 Jan. 2003.
[12]Jendernalik, W.and Szczepanski, S., “A CMOS OTA-C channel-select filter for mobile receiver”, Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on,26-28 June 2002.
[13]Richard Van Nee and Ramjee Prasad, “OFDM for Wireless Multimedia Communications”, Oct. 1999.
[14] Frode BohagenandHenrik Holmboe Bjornsen, “Adaptiv koding og modulasjon IEEE802.11a og HIPERLAN/2”, Nov. 2002.
[15] 江學敏, “應用於IEEE802.11a直接降頻式通道選擇低通濾波器”,中華大學電機所,JUL. 2003.
[16]Brian DessentandTina Smilkstein, “A Two-Stage Fully Differential OperationalTransconductance Amplifier”,University of California,EE240 Term Project ReportProfessor B. E. Boser, Spring 2001.