3-D Integration Project Quarterly Report

3-D Integration Project Quarterly Report

Neil Goldsman, Zeynep Dilli

1. Overview

We designed and submitted two chips to the MOSIS fabrication service in June 2002 and one in October 2002. The first chip used AMI Semiconductor’s 1.6 m feature size technology, AMI ABN (lambda=0.8). The other two chips used the 0.6 m technology, AMI C5N/F (lambda=0.3). The first two chips had similar structures on them to examine the detrimental effect of bonding pads and pins on circuit performance and possibly to conduct some interference tests. The third chip has been designed with post-fabrication processing in mind, to integrate pairs of this chip vertically.

For the first two chips, we ordered two packaged and three unpackaged chips. For the last run, we ordered one packaged and four unpackaged chips.

The circuitry on the chips, to be detailed below, consist of specially designed ring oscillators, supporting test and on-chip built-in diagnostic structures, and 3-D integration structures.

Using structures on the first 0.6 micron chip, we have demonstrated that the need to go out to the PCB and come back on chip impedes circuit performance considerably compared to a simple planar circuit. With our work on the new 0.6 micron chip, expected back from fabrication in December, we hope to demonstrate that three-dimensional integration will demonstrate comparable performance to a planar circuit and a marked improvement over the speed of a signal-goes-out-of-chip type circuit.

The full layout for the 1.6 m chip is shown in Figure 1. The layout for the first 0.6 m chip is shown in Figure 2, and for the second one, Figure 3.

1. Ring Oscillator Structures and Counters

In conventional circuit design that requires the functionality of more than one commercially available integrated circuits, the communication through the circuits are usually handled by the connection chain of circuit  bonding pad  bonding wire  pin  PCB line  pin  bonding wire bonding pad  circuit. This arrangement adds significant parasitic capacitance and inductance to the communication link, and has detrimental effects on both circuit speed and power dissipation. Moreover, the need to drive the large capacitance of bonding pads (this is large relative to in-chip capacitances) requires large-transistor “buffer”s, usually a chain of progressively larger inverters, as the last stage of any circuit component that has to have an output to the outside world, which wastes real estate on chip and adds delay to the output stages of circuits.

To observe these effects in a circuit whose behaviour is simple and easily quantifiable, we have designed and laid out basic ring oscillators for each of the three chips. In the June 2002 ABN and C5N chips, there were two types ring oscillators laid out for these purposes. The first ones were “internal”, or planar, ring oscillators, formed by directly connecting the output of and inverter to the input of the next one. The 1.6 m and 0.6 m oscillators had 19 and 31 stages, respectively. The simulated operation frequencies for these inverters were 63.3 MHz for the first chip and 132.45 MHz for the second. The 0.6 m inverter is depicted in Figure 4.

The output stages of these ring oscillators are connected to frequency-divider-setup counters in both chips. These counters serve a dual purpose. First is to reduce the frequency of the output of the ring oscillators, and thus, aiding the ease of measurement. The second is to avoid loading the output stages of the ring oscillators directly by the bonding pad, wire, and probe capacitances, for a better comparison with the external ring oscillator operation, to be described below. Thus these counters serve as on-chip test structures.

The June 1.6m chip carried a 4-bit counter made of T-flip flops. The 0.6m chips carry 6-bit counters made of D-flip flops. The D-flip flop design and layout are given in Figure 5; the schematic of the 6-bit counter is given in Figure 6.

The second type of ring oscillator present in the June chips were “external” ring oscillators, which are individual inverters getting their input from one bonding pad and sending their output to another pad. This way, there would be two bonding pads (and the out-of-the-chip connection chain) between each stage of the ring oscillator when these inverters are linked externally to form it. On the layouts of these chips, in Figures 1 and 2, these inverters can be seen as lining the left side of the layout, going from the ground pin to the Vdd pin.

The results obtained from the 0.6 m chip, measured on a breadboard using the 1-pF input capacitance active probe from Tektronix, are as follows:

Internal Osc. / External Osc. / One-stage delay
112 MHz (31-stage)
(equivalent to 1.16 GHz for 3 stages) / 398 KHz (11-stage)
(equivalent to 1.46 MHz for 3 stages) / ~330 ps for internal, ~330 ns for external devices

Thus we can observe that going through the out-of-chip connection chain slows down the circuit by about 800-fold.

The 11-stage external ring oscillator of the 1.6 m chip ran at 732.7 kHz on a PCB measurement with the active probe. It would run at 278 kHz on the breadboard with a 25-pF input capacitance BNC probe. In these measurements, in an effort to determine which part of the capacitive effect arose from the breadboard itself, a capacitive load vs. rise/fall/delay times table was created with additional load capacitances inserted between the output of an inverter and the ground on the breadboard. Using this table and extrapolating, it is possible to deduce that the load capacitance of the bonding pad+bonding wire+pin+breadboard+active probe ensemble is about 15 pF. The probe is claimed to have 1 pF load. For the pad itself, Cadence extracts a capacitance of 0.24 pF, however, this does not include the capacitances of the quite large ESD protection transistors. We have planned to repeat this experiment using the PCB to deduce the capacitance of the pin-PCB line connection chain. We could not get a meaningful result out of the internal ring oscillator of the 1.6 m chip.

In the October chip, we once again implemented the 31-stage internal ring oscillator with the 6-bit counter as its output stage. However, we also implemented a structure that will be post-fabrication processed into a 3-D ring oscillator. This structure, shown Figure 7, consists of six groups of inverters (five with five and one with six inverters each) placed deliberately around the symmetry axis of the layout so that when two chips made from this design are taken together, one is flipped over and placed over the other, with the correct connections these inverters will form a ring oscillator. The output of this oscillator also goes to a 6-bit counter.

The 3-D bonding pads used in this structure are comprised of three layers of metals, connected with vias, squares with 12 m sides. Their to-substrate capacitance is of the same order of magnitude as the input capacitance of a minimum size inverter in this technology. Therefore, while the 3-D ring oscillator formed this way is expected to be slower than the full planar oscillator, we do not expect a great detrimental effect to speed. Moreover, we expect the performance of this oscillator to be better than the external oscillators of the June chips.

1. Other Structures on the June chips

Small Counters The 1.6 m chip houses two small, 2-bit counters in independent frequency-divider configurations. These counters have the exact same design and schematic, but slightly different layouts. The difference lays in the compactness of the layout and the path traversed by the clock signals. Feeding them with identical count signals, we investigated possible differences in performance. Measurements on a PCB with the active probe yielded the following results:

Rise time (ns) / Fall time (ns) / tPLH (ns) / tPHL (ns)
Counter A / 50.51 / 69.09 / 27.5 / 72
Counter B / 37.44 / 62.21 / 37 / 61

There is, therefore, a measurable difference in operation arising from layout differences alone. The exact effects taking place are still under investigation.

Pn-junctions Both chips had an p+/n-well diode built in to be tested. This is one of the possible diode configurations that can be used while laying out an optical detector cell or a pixel in conventional CMOS technology. Rectification was observed, with the characteristic diode IV curves, for both.

Large inverters Both chips had “reality-check” inverters laid out independently from the external ring oscillator inverters, with somewhat larger feature sizes. These inverters were tested operational for both designs, with rise and fall times smaller than the minimum-size inverters’ times for the corresponding technology, as could be expected from their higher current-driving capabilities.

Crosstalk measurement setup On the 0.6 m chip, two D-flip flops sharing the same clock signal are connected in a two-stage latch configuration (the Q output of the first one to the D input of the other). The connection between them is a rather long and snaking metal1 line, as can be observed in Figure 8. Winding along with this line is an input line for an ordinary inverter, shown in the figure below the two flip-flops. This circuit is designed to observe possible fluctuations in the data line between the two flip-flops when an input signal is applied to the inverter, with the possibility that the second ff might latch an incorrect value. Test work is still under progress.

1. Other structures on the October chip

“External” ring oscillator This layout features a three-stage ring oscillator, close to the top edge of the die to the right of the Vdd pad, that is similar to the external ring oscillators of the previous chips in that the bonding pads still load the inverters that form its stages. However, in this oscillator the connections between the inverters are direct and internal, with the bonding pads serving as only loads, not connection stages. This structure aims at measuring the effect of the bonding pads more isolated from those of the other stages of the out-of-chip connection chain. This structure is displayed in Figure 9.

XOR with output buffer An XOR gate is useful in applications that require measuring the relative phases of two signals or testing if two signals are identical. We designed, simulated and laid out an XOR gate for use in such measurements in the future. For this XOR to drive the extra capacitance of the bonding pad, through which its output will be measured, a four-stage buffer comprising of progressively larger inverters was connected to its output. This structure is visible close to the lower right corner of the chip.

Phase delay measurement setup These are two pairs of inverters whose outputs are sent to corresponding XOR gates. In both pairs, the input paths to the inverters from bonding pads are nearly equal. In one pair, the paths from the outputs of the inverters to the inputs of the XOR are also equal. In the other, one path meanders, adding an extra distance to the signal path approximately equal to that added to the 3-D ring oscillator with signals going to and coming back from the connector pads. The XORs, once more buffered with progressively larger inverters to their outputs at bonding pads, will detect the phase difference between these two paths. This structure is placed on the bottom left corner of the chip and depicted in Figure 10.

More 3-D circuits At the top part of the layout, two D-flip flops are laid out symmetrically so as to be connected in three dimensions in a 2-bit counter setup. Right below that, identical flip flops are connected into a planar 2-bit counter. To the right and left of this counter there are two inverters with 3-D connection pads furnished at input and output for the creation of a 3-D buffer. To the right, there is a single planar buffer. These structures are for the purposes of performance comparison.

Large NMOS Close to the bottom right corner of the chip, there is a NMOS 10 times the minimum size (W=150 m, L=60m). The source is shorted to the body, which is at ground level, as with all digital NMOSes on the chip. The gate and drain are connected to bonding pads. We hope to conduct gate noise measurements with this FET.