FPGA Developer 9/05 – draft11/2/20181
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FPGA Developer
This Month’s Theme: FPGA Verification
Chip Design magazine –
ExtensionMedia, Inc. –
October 18, 2005
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Welcome to the October edition ofFPGA Developer. This e-newsletter complements Chip Design magazine by providing the latest FPGA and Structured ASIC news, opinions from industry experts, and timely technology articles. See below for subscribe andunsubscribe options.
Today's Table of Contents:
0.Editor’s Note –Getting it right the first time
1. Making Single Pass FPGA Design a Reality
2. A Wake-Up Call for FPGA Verification
3.FPGAs Make Music
4.650MHz Prototype Foreshadows Early Release of 1+GHz FPGA
5.FPGA Conversion Vendor Deepens Portfolio
6.Fastest FPGA Power-Up Solution
7.FPGAs Enable Software Defined Radio Applications
8. Expanding Device Support Strengthens Vendor Independence
9.In-Depth Coverage Links
FPGAs and Structured ASICs: New Solutions for Changing Market Dynamics
You Can't Get There From Here: A Yankee's Lessons about EDA
10. Online FPGA Resources
11. New Book
FPGA Implementations of Neural Networks
12. Happenings
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0. Editor’s Note
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Getting it right the first time
By Jim Kobylecky, Editor
Sometimes I go straight from being irritated with balkyhigh tech devices to being amazed that they work at all. Compared to tracing simple circuits in first term Scienceclasses, today's designers have to work through many layers of abstractions to reach the reality beneath. It's kind of like expecting Michelangelo to sculpta million submicron Davids while wearing boxing gloves.
So in this issue of FPGA Developer, we take the gloves offandreexamine the verification process. How do our current tools help us getFPGA designs right the first time? How do theymake things even harder?Is it our preconceptions about tools and methodologies that's getting in the way? We start the questions inour exclusiveindustry Viewpoints and carry the discussion into our In-Depth links. And, as always, we'llround out the issue with the latest FPGA and structured ASIC news and events.
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1.Viewpoint – Exclusive
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MakingSinglePass FPGA Design a Reality
By Andy Haines, Vice President of Marketing, Synplicity Inc. (
Single pass FPGA design has seemed an intangible ideal for designers ever since the capacity of these devices has reached into the hundreds of thousands of gates. With the imposing complexity of interconnect-dominated delay, and the difficulty of predicting delay prior to placement and routing, this ideal would seem less tangible now than ever. In fact, it has been posited that a multi-pass approach, involving back-annotation and iterations to reach timing closure, is here to stay.
But, those not quite ready to resign themselves to a life of laborious back-annotation and iteration might ask, “What does it really take to achieve a single pass FPGA design flow?” The answer is design technology.
At the heart of the solution is a more FPGA-aware approach to pre-route timing estimation. Synthesis algorithms that operate on the traditional ASIC assumption that proximity and wire-load models sufficiently predict routing delay are woefully inadequate for today’s FPGAs. Unlike ASICs, FPGAs have fixed routing resources, for which the classic ASIC proximity-based timing estimation is fundamentally inaccurate. Without accurate timing correlation to final results, designers find themselves in an endless loop, solving one critical path just to have another one pop up.
The problem with a proximity-based approach can be illustrated with an example of a typical commute to work. In this analogy, FPGA routing resources represent the streets and freeways, and the endpoints of the critical path represent the home and office. Though the most direct route to the office might seem the quickest, it might actually be quicker to go a couple of blocks out of the way to access a freeway. Similarly, in an FPGA, some direct routing resources are faster and more likely to be actually routed than more local switch matrices – basing timing estimates on proximity and not the actual resources available will thus return an erroneous result.
Design technology that delivers accurate timing estimation, and hence single-pass design, hinges upon two key elements: intelligence of the specific FPGA architectures, and placement and routing capabilities during timing estimation. In order to accurately estimate routing delays prior to actual placement and routing, the synthesis environment must have intelligence of the pre-existing wires, switches and placement sites for the various architectures being considered. Thus, a massive database, represented as a detailed routing resource graph, is a cornerstone of a single-pass solution. It provides the information necessary to measure delay based on actual delay and availability of resources as opposed to just proximity.
The other element of single-pass-enabling design technology is tools that comprehend this resource intelligence and translate it into accurate timing. Within the physical synthesis environment, routing, placement and optimization capabilities translate this information into intelligent timing estimates. Within such an environment, iterations to reach a timing prediction that correlates with final results can happen completely transparently to the designer, returning a better result and eliminating the need for manual intervention.
This technology, called graph-based physical synthesis, embraces a fundamental reality in today’s nanometer design world: FPGA design solutions must fully comprehend the physical properties of the specific target architecture to be effective. Designer productivity and design results can be assured only by moving beyond the conventional ASIC approach to one that addresses the unique attributes of FPGAs. Applying intelligence of those architectures with tools that can effectively apply that information can make the single pass design ideal a very tangible reality.
Comments about this article? Share you thoughts by contacting oureditorial director: .
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2. Viewpoint – Exclusive
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A Wake-Up Call for FPGA Verification
By Thomas L. Anderson, Director of Technical Marketing, Verification Group, Synopsys, (
“I don’t need to worry about verification; I can just re-program to fix any bugs.”
For decades, this has been the mantra for most designers of FPGAs and other programmable devices. To a considerable extent, this statement has been true. Certainly these designers have a big advantage in not having to go through the full mask-generation and fabrication process for standard cell or custom design, or even the abbreviated process for gate arrays, in order to fix bugs. Indeed, the ability to fix bugs almost instantly is one of the most seductive features of FPGAs.
I’ve been marketing verification IP and EDA verification tools for ten years now, and the vast majority of my customers have been designing ASICs or custom chips. Sure, we’d try to convince the FPGA users, and they were usually willing to listen to a presentation, but nine times out of ten they would just thank us and repeat the mantra.
However, in the last few years I have seen a gradual but noteworthy shift in thinking. Nothing has changed the underlying value of FPGAs: it’s still the case that bugs can be fixed quickly and inexpensively. The problem, of course, is that one needs to detect and diagnose bugs in order to fix them. Ay, there’s the rub.
Detecting the bugs is the lesser of the two problems, since running FPGAs in prototype systems tends to stress the designs well. There’s always a risk that the lab tests won’t hit every corner case that might have been exercised by an effective verification environment. A good example is an error condition that might not occur in a particular prototype setup but that would be easy to inject in a modern simulation testbench.
Diagnosing the detected bugs can be a really hard problem. Although FPGA architectures may inherently offer more visibility into internal signals than fabricated chips, the process of going from a detected system-level error to isolating the actual bug in the design RTL source code (or, perish the thought, a gate-level schematic) is challenging.
I recall a visit I made a few years ago to a prospective customer designing systems in the networking space. They had a very simple verification environment—a few PCs running an inexpensive simulator with only some basic, hand-crafted “sanity tests.” They relied on programming their FPGAs early in the project and doing the bulk of their verification while running in their prototype systems, which had always worked just fine in the past.
They were trying to get their next-generation system working in the lab. The engineers were finding plenty of bugs, but they were going crazy trying to diagnose them. Whenever they found a problem, they would take their best guess as to where the bug might be and re-program the FPGAs to bring out some internal signals to watch on their logic analyzers. Of course, they didn’t always guess right and so the process was highly iterative.
They had been debugging in the lab for more than six months and were nowhere near having a working system. They were at severe risk of missing their market window and ceding the next generation to their competitors, so they were desperately talking to EDA vendors for ideas on how to get out of their jam. I offered some suggestions, but they decided that they could not afford the investment in workstations and more advanced tools, so they soldiered on. I’m not quite sure whatever happened to their project, but the company seems to have disappeared.
This story is surely not unique. As FPGA-based systems grow in complexity, the size of the devices grows and the ability to diagnose bugs found in the lab diminishes. In response, FPGA design teams are increasingly adopting verification environments that look more like those of ASIC and custom chip projects than those of their past.
Some FPGA designers are using code coverage and functional coverage to get a handle on what is actually happening in their design. Assertions in their code, sometimes synthesized into the FPGAs as well, are improving bug diagnosis by helping to pinpoint unexpected behavior. A few teams have even adopted a full constrained-random, coverage-driven verification approach that rivals the sophistication of modern ASIC verification. The adoption of all these techniques is being accelerated by the availability of SystemVerilog, the standard design and verification language that subsumes Verilog, VHDL, assertions, and testbench languages.
The more I talk with customers, the more I’m convinced that FPGA designers can no longer risk their schedules by sticking their heads in the sand when it comes to verification. Detecting, diagnosing and fixing bugs in million-gate chips are challenges regardless of the silicon technology. Fortunately, FPGA designers can draw on the considerable experience of their peers, as documented in the recently-published Verification Methodology Manual for SystemVerilog. Facility with advanced verification techniques is a requirement for today’s FPGA design teams.
Comments? Share your thoughts by contacting the Editorial Director at .
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3. News: FPGAs Make Music
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Lab X Technologies, LLC, and Xilinx are enabling digital audio products for touring musicians. The ESX EtherSound Module leverages the programmable features of Xilinx Spartan-3 FPGAs to develop a flexible architecture that can adapt to the many evolving Ethernet standards of the audio industry. It provides an elegantly simple and open standard for networking digital audioin professional applications such as live concerts and broadcast productions. The programmable FPGAs allows Lab X to customize the “soft core” of ESX and provide manufacturers with functionality for user interfaces/external circuitry control (GPIO), signal processing, and huge amounts of audio I/O.
Lab X Technologies , LLC
Xilinx
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4. News: 650MHz Prototype Foreshadows Early Release of 1+GHz FPGA
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Achronix Semiconductor Corporation reports the first successful prototype of its -ULTRA line of high speed FPGAs. Based on a commercially available CMOS technology, the successful prototype operates at lower power than other state-of-the-art FPGAs. Having accomplished this using an 180 nm fabrication process, the company expects to double its performance at 90nm. The company believes that by offering performance of well over 1GHz by mid-2006, it will open up a previously inaccessible markets for FPGAs. Achronix plans to release the first product in the Achronix-ULTRA operating at speeds over 1 GHz line in the second quarter of 2006.
Achronix >
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5. News: FPGA Conversion Vendor Deepens Portfolio
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AMI Semiconductor has fully integrated the FPGA-to-ASIC conversion assets of newly acquired Flextronics Semiconductor. The company’s Structured Digital Product business unit, which has specialized in FPGA-to-ASIC conversions for more than 15 years, had already supported array and cell-based structured digital technologies. Its XPressArray familysupports specific drop-in replacement FPGA intellectual propertyand seam-less turn-key design services.With its recent acquisition,AMIS adds two new families of quick-turn array-based architecturesand additional design services. The Flextronics business model targets lower density applications, complementingthe company's support of mid- to high-density applications.
AMI Semiconductor >
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6. News: Fastest FPGA Power-Up Solution
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Actel Corporation has shown that its nonvolatile FPGAs offer up to 4000 times better power-on response time than competing SRAM-based FPGAs. These live at power-up (LAPU) single-chip FPGAs eliminate the need for additional power-up and initialization circuitry. The LAPU nature of the company's nonvolatile FPGA technologies make them optimal solutions for automotive, consumer, medical, military and other applications that require immediate operation as well as low total system cost. Live at power-up FPGAs are the only devices that can assist in system start-up tasks, system configuration and supervision during voltage ramp-up, which can result in total system cost savings of 50 percent or more.
Actel >
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7. International News: FPGAs Enable Software Defined Radio Applications *******************
Spectrum Signal Processing Inc. has added the XMC-3311 high speed transceiver XMC/enhanced PMC module to its flexComm software defined radio product line. The XMC-3311 supports wide bandwidth processing applications including commercial and military satellite communications, signals intelligence and electronic warfare. Itincorporates a Xilinx Virtex-4 FPGA tosimplify algorithmic coding and provide higher performance, higher density and greater memory capacity for processing. Spectrum provides a high-speed packet interface that sets up physical and logical channels to route data flow from the FPGA through the module's fabric crossbar to the XMC connector. The company expects that the packet interface alone will save its customers hundreds of hours of development time.
Spectrum Signal Processing Inc
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8. International News: Expanding Device Support Strengthens Vendor Independence
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Altium Limited, a leading developer of Windows-based electronics design software headquartered in Australia, announced supportof Lattice Semiconductor’s LatticeEC and LatticeECP FPGA devices in its Altium Designer, a unified application that incorporates all the technologies necessary for complete electronic product development within a single application. The software's device- and vendor-independent environment allows developers to easily retarget FPGA-based designs to any supported device and delay final device selection until much later in the design process. The Lattice devices join the wide array of Altera, Xilinx and Actel FPGAs and CPLDs already supported by Altium, strengthening the company’s FPGA vendor-independent position.
Altium Limited >
Lattice >
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9.In-Depth Coverage Links
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To get a device functioning correctly the first time it's imperative to avoid the additional costs and delays of re-spinning the ASIC. Verifying a design using state-of-the-art 90 nm FPGAs for prototyping reduces risk. The risk can be further reduced by migrating FPGA-verified design into structured ASICs. As you will see in this iDesign article: "FPGAs and Structured ASICs: New Solutions for Changing Market Dynamics," this development flow can bypass the pain and expense of traditional ASIC development while still meeting cost, performance and power requirements.
Featured Story >
Feeling that chip design and EDA have not kept pace with the demands of exploding complexity, this article tries for a fresh perspective. Do real life "Down Easter" lessons really apply to hardware design? More than you might think. For a little warm fire and cold logictry: “You Can't Get There From Here: A Yankee's Lessons about EDA.”
Featured Story >