The Following Table Shows the Revision History for This Document

Zynq UltraScale+ MPSoC ZCU102Getting Started Guide
Initial Draft
Xilinx Answer 66249, UG### (v 0.4) Dec15, 2015

Revision History

The following table shows the revision history for this document.

Date / Version / Changes
15th Dec, 2015 / 0.1 / Initial Draft.
15th Dec, 2015 / 0.2 / Updated with PetaLinux BSP folder name
15th Dec, 2015 / 0.3 / Added Patch locations and launch SDK from Vivado
18th Dec, 2015 / 0.4 / Added Critical Known Issues table

Initial Draft

Preliminary Zynq UltraScale+ MPSoC Software Developers Guide15-Oct-18

Table of Contents

Revision History

Preface: About this Guide

Intended Audience and Scope of this Document

Pre-Requisites

Introduction

ZCU102 platform bring up models

Tool setup

Downloads

PS-only User model, without High-speed interfaces

HDF generation using Vivado

SDK

PetaLinux

PS-only User model, with High-speed interfaces

HDF generation using Vivado

SDK

PetaLinux

PS design with PL interface

To be added later

References

List

Preface: About this Guide

The Zynq UltraScale+ MPSoC,ZCU102 Getting Started Guideprovides the build instructions for various images such as bitstream, fsbl, kernel etc. It is targeted to the ZCU102 platform.

Intended Audience and Scope of this Document

This Getting Started Guide for the Zynq UltraScale+MPSoC ZCU102 platformis intended to assist Software Developers and System Architects to:

Understand the procedures involved in designs based on High-speed interfaces (ex: PCIe, SATA, USB3.0, Ethernet and Display Port)
Understand the steps to be followed for development cycles at various stages (ex: Vivado, SDK, PetaLinux).

Pre-Requisites

This document assumes that you are:

Experienced with embedded software development
Familiar with ARMv7 and ARMv8 architecture
Familiar with embedded software development tools like IDEs, Compilers, Debuggers and Operating Systems

Introduction

ZCU102 platform bringup models

Zynq UltraScale+ MPSoC supports five High-speed interfaces:

Ethernet
PCIe
USB3.0
SATA
Display Port

Zynq UltraScale+ MPSoC, ZCU102 platform development cycles are broadly divided into three categories.

PS-only user model, without High-speed interfaces
PS-only user model, with High-speed interfaces
PL user model (not covered in this document)

Tool setup

This guide is based on Xilinx tools:

SDK
Vivado
PetaLinux

The following discussion is based on above tools of version 2015.4.

Downloads

This guide refers to various tools and patches that are used in various build methods. The download paths for them all as below:

Tool / Download Path
Full Vivado+SDK HLx Install /
SDK Standalone Install /
PetaLinux Tool and ZCU102 BSP /
ZCU102 FSBL Patch for SDK /
ZCU102 Vivado Project files /
Vivado Processing System patch /
SDK MYVIVADO Patch /

Critical Vivado 2015.4 Known Issues

In addition to the patches above, consult the Zynq UltraScale+ MPSoC Solution Centerfor current issues.

A limited selection of critical issues most relevant to ZCU102 users are collected below:

Xilinx Answer / Title
66183 / Processing System IP - Release Notes and Known Issues
66218 / TCL/debugger flow is not working due to difference between psu_init.c and psu_init.tcl
66219 / Bringing Processors out of reset by configuring the Processor Block level software controlled reset registers in JTAG mode
66295 / PS-PL AXI Interfaces do not function correctly at 64- or 32-bit widths
66283 / ZCU102 I2C EEPROM driver examples do not complete

PS-only User model, without High-speed interfaces

HDF generation using Vivado

The application development in this model does not need any specific hardware platform. The SDK tool provides pre-defined hardware platform. Hence there is no need for Vivado specific instructions.

SDK

The SDK flow is as follows:

Launch XSDK tool
Linux OS:

$ xsdk

Windows OS:

TBD

Create a new workspace. Provide a folder name in the box Workspace
Click on: File  New  Application Project
Type “zynqmp_fsbl” in the box Project Name
Click on: Target Hardware  Hardware Platform ZynqMP_ZCU102_hw_platform (pre-defined)
Click on Next
Select Zynq MP FSBL in the list “Available Templates”
Click on Finish
This completes the project creation for the ZCU102 platform
In caseany of the source files (FSBL or BSP) need to be modified, browse to the file, make the change and save the file (saving the file will automatically build the project).
The ELF file will be present in the Debug folder inside the FSBL folder.

PetaLinux

Setup the PetaLinux environment

$ source <install folder>/petalinux-v2015.4-final/settings.sh

Create a project workspace. The template (Xilinx-ZCU102-v2015.4-final.bsp) comes along with the PetaLinux BSP installation.

$ petalinux-create --template zynqMP -t project -s Path-to-BSP-folder>/Xilinx-ZCU102-v2015.4-final.bsp

$ cd Xilinx-ZCU102-2015.4

Build the FSBL image.

$ petalinux-build -c bootloader

The ELF file will be present in the “<project folder>/images/linux” folder.
Build the remaining boot images.

$ petalinux-build

All boot images are placed in the folder: images/linux

PS-only User model, with High-speed interfaces

HDF generation using Vivado

The below steps are needed to create a PS-only design that uses High-speed interfaces

Linux OS:

Install the Processing System IP patch from Xilinx Answer 65982
Install the SDK MYXILINX patch from Xilinx Answer 66198
Launch Vivado and create hdf

Launch Vivado using the following command:

$ vivado

Windows OS:

Instructions in Vivado GUI:

In the Vivado window, select Tools -> Run Tcl Script…
Browse the design Tcl script (based on the desired GT configuration, shown below) and click OK.

SEL (S3,2,1,0) / ICM Settings
(Lane 0,1,2, 3) / Tcl file to be sourced in Vivado
0000 / PCIe.0, PCIe.1,
PCIe.2, PCIe.3 / zcu102_gt0000_clksivdef_ddrauto2133.tcl
1111 / DP.1, DP.0, USB, SATA / zcu102_gt1111_clksivdef_ddrauto2133.tcl
1100 / PCIe.0, PCIe.1, USB, SATA / zcu102_gt1100_clksivdef_ddrauto2133.tcl
1110 / PCIe.0, DP.0, USB, SATA / zcu102_gt1110_clksivdef_ddrauto2133.tcl

Right click on the design (In the Block design frame and sources tab), select Create HDL Wrapper… and click OK.
In the same Vivado window, Select File -> Export -> Export Hardware… click theGenerate Output Products button. Then click OK and then again OK.
The HDF file is now created, the path of which is shown in the Tcl console window in Vivado

Launch SDK

Launch SDK, select File-> Launch SDK

SDK

The SDK flow below describes how to launch SDK and create FSBL based on the new hardware platform (PS with High-speed interfaces). SDK has been launched from Vivado.

Apply the ZCU102 FSBL patch to SDK:

The FSBL source code that comes by default with SDK does not contain code for initializing the High speed interfaces. A patch is provided separately to perform the same.
Follow the patch directions in Xilinx Answer 66197

CreateHardware platform:

Select FileNewApplication Project to open the "New Project" window, and provide the name for the FSBL project
In the "Target Hardware" section, select a new hardware platform that supports SERDES configuration, as described below:
Click on "New", to create a new hardware platform.
In the next window (New Hardware Project), enter the "Project name"
Under the "Target Hardware Specification", click on browse
Select the HDF file and a new hardware platform is created.

This new platform contain SERDES functionality to be used in design, created using Vivado.

Create FSBL:

In the "New Project" window, select the processor psu_cortexa53_0/psu_cortexr5_0
If the Processor selected is psu_cortexa53/psu_cortexr5_0, select Compiler to be either 64-bit (default) or 32-bit from drop down menu
Click Next and select "Zynq MP FSBL"
Click "Finish" to generate the A53/R5 FSBL. This populates the FSBL code and also builds it (along with BSP)
Change the compiler optimization flag from O0 to O2. In SDK, use the following procedure to change this:
Right click theFSBL application project and select "C/C++ Build Settings"
On the “Tool Settings” tab, select “Optimization”
For the “Optimization Level” drop down menu, change from "None (-O0)" to "Optimize more (-O2)"
Optional operations:
Debug prints in FSBL aredisabled by default(except for the FSBL banner). To enable debug prints, define symbol: FSBL_DEBUG_INFO
In SDK this can be done by: right click on FSBL application project -> select“C/C++ Build Settings” -> “Tool Settings” tab -> Symbols (under ARM A53 gcc compiler)
Click on Add (+) icon and Enter the Value:FSBL_DEBUG_INFO, click on "OK" to close the "Properties" screen
In caseany of the source files (FSBL or BSP) need to be modified, browse to the file, make the change and save the file (saving the file will automatically build the project).
The ELF file will be present in the Debug folder inside the FSBL folder.

PetaLinux

Setup the PetaLinux environment

Set the PCW patch path to the MYVIVADO environment variable

$ setenv MYVIVADO <path to PCW extracted directory>/AR65982_vivado_2015_4_preliminary_rev2/vivado

Create a new workspace

$ source <install Plnx folder>/petalinux-v2015.4-final/settings.sh

Create a project workspace. The template (Xilinx-ZCU102-v2015.4-final.bsp) comes along with the PetaLinux BSP installation.

$ petalinux-create --template zynqMP -t project -s <Path-to-BSP-folder>/Xilinx-ZCU102-v2015.4-final.bsp

$ cd Xilinx-ZCU102-2015.4

CreateHardware platform:

Select a new hardware platform that support SERDES configuration, as below:

Use the HDF file which contain SERDES functionality to be used in design, created by Vivado.

$ petalinux-config --get-hw-description=<Folder name contain new hdf file> --oldconfig

Apply ZCU102 FSBL patch to PetaLinux Project:

Unzip theXilinx Answer 66197 ZCU102 FSBL “.zip” into a folder (ex: patch)
Copy the specific FSBL patch file (i.e. xfsbl_initialization.c ) to the FSBL folder in the ZCU102 project

$ cp –r <path to the directory of FSBL>/sw_apps/zynqmp_fsbl/src/xfsbl_initialization.c Xilinx-ZCU102-2015.4/components/bootloader/zynqmp_fsbl/.

Build the FSBL image.

$ petalinux-build -c bootloader

The ELF file will be present in the “<project folder>/images/linux” folder.

Build other boot images.

$ petalinux-build

All boot images are placed in thefolder: images/linux

PS design with PL interface

To be added later

References

List

Below is a list of references and Xilinx Answer Records containing more details

PetaLinux documents
PetaLinux Tutorial
PetaLinux Reference

Zynq UltraScale+ Software Developers Guide