Level 1 Muon Trigger

Level 1 Muon Trigger

Technical Design Report

K. Johnsggg

Version 1.0

6/23/97

1. Introduction...... 3

2. Overview...... 4

2.1 Level 1 Central Fiber Tracker Trigger...... 4

2.2 Muon Detector System...... 4

2.3 Accelerator Timing...... 5

2.4 Level 1 Muon Trigger...... 5

3. Muon Trigger Cards...... 17

3.1 Serial Link Daughter Boards (SLDB)...... 18

3.2 Muon Centroid Cards (MCEN)...... 18

3.3 Muon Centroid Crate Manager (MCCM)...... 18

3.4 Muon Trigger Cards (MTCxx)...... 18

3.5 Muon Trigger Flavor Boards (MTFB)...... 18

3.6 Muon Trigger Crate Manager (MTCM)...... 18

3.7 Muon Trigger Manager (MTM)...... 18

4. Muon Trigger and Muon Centroid Crates...... 18

5. Muon Trigger Simulation...... 18

6. Outstanding Problems...... 18

1.Introduction

We describe the Level 1 Muon Trigger (L1MU) system for Run II of the Dcolliding beam experiment at the Fermilab Tevatron. The L1MU system identifies muon candidates to the Trigger Framework (TF) in time for the Level 1 (L1) trigger decision (presently 3.56 s at the TF location). Muon candidates are identified using combinatorial logic that makes use of tracks from the Level 1 Central Fiber Tracker (L1CFT) trigger and hits from all muon detector elements. The muon detector elements include both drift chambers and scintillation counters. The Run II design luminosity is 2x1032 / cm2 / s. Crudely speaking, the design goals of the L1MU are to provide a 1 kHz high PT (PT > 10 GeV/c) single muon trigger and a 2 kHz low PT (PT > 1.5 GeV/c) at the Run II design luminosity. The total L1 bandwidth (all triggers) at 2x1032 / cm2 / s should not exceed 10 kHz.

The L1MU satisfies the following requirements:

Delivers an L1MU decision to the TF at 3.3 s after Bunch Crossing (BC)

Transmits an L1MU decision for every BC not occurring in the Synch Gap

Operates with 132 or 396 ns BC times

Synchronizes all inputs to the Muon Trigger (MTCxx) Cards

Provides buffer storage for input and output data pending an L1 decision from the TF

Provides 16 buffers for data storage pending a Level 2 (L2) decision from the TF

Provides 8 buffers pending readout of data to Level 3 (L3)

Deadtimeless operation

Field programmable trigger logic

Online and offline monitoring

Fully documented

A block diagram of the L1MU system is shown in Figure 1. There are three custom VME crates of muon trigger cards corresponding to the central (CF), north (EFN), and south (EFS) geographic regions of the D detector. The VME crates reside on the detector platform and are thus inaccessible during data-taking.

Within each crate there are eight muon trigger “05” cards (MTC05 cards) and eight corresponding muon trigger “10” cards (MTC10 cards). Each detector region is divided into octants and each MTC05 and MTC10 card makes local trigger decisions within one octant.. The names “05” and “10” do not represent different levels of triggering but rather distinguish between those trigger decisions made primarily using L1CFT tracks and scintillator hits and those made primarily with wire chamber hits and scintillator hits. The muon trigger uses both “05” and “10” trigger decisions in a user defined manner to determine whether good L1 muon trigger conditions have occurred.

When referring to the MTC05 and MTC10 cards non-specifically we use the term MTCxx. A daughter board on the MTCxx card determine its “flavor”. Information is sent to the L1MU from three sources: detector front end cards, L1CFT cards, and MCEN cards. This information is transmitted at 1060 Mbits/s over coaxial cable using the AMCC S2032/2033 serial link chip set. Each MTCxx card accepts sixteen inputs. Preliminary assignments are given in Tables 1-6.

The trigger logic uses three types of information: tracks from the L1CFT, hits from trigger scintillation counters, and hits from tracking chambers. Hits from the trigger counters are valid only within an approximately 25 ns time window to reduce out-of-time background. Hits from the tracking chambers are combined into centroids (“stubs”) which reduce low energy background and background not originating from the interaction region. These centroids are further “confirmed” (checked to be consistent) with trigger counter hits.

In the central (CF) region, the trigger logic uses hits from the Aphi and Bottom B/C trigger counters in coincidence with L1CFT tracks. The phi coordinate of the Aphi counters is matched with the phi coordinate at the outermost CFT layer of L1CFT tracks. Two layer coincidences between centroids in the three layers proportional drift tubes (PDT’s) can also be included in the trigger decision. In the forward (EFN and EFS) regions, the trigger logic uses hits from the A, B, and C Pixel trigger counters in coincidence with L1CFT tracks. Two or three layer coincidences between centroids in the three layers mini-drift tubes (MDT’s) are also included in the trigger decision. In the forward extension (EFNX and EFSX) regions, the trigger logic requires three layers of Pixel trigger counters and three layers of MDT centroids.

2.Overview

Three distinct types of information are input into the L1MU system: tracks from the L1CFT, hits from muon trigger scintillation counters, and hits from muon tracking chambers. These elements are briefly described below. The accelerator beam crossing structure is also discussed. The L1MU system is subsequently summarized.

2.1Level 1 Central Fiber Tracker Trigger

The Dtracking system consists of an inner Silicon Tracker (ST) and an outer Central Fiber Tracker (CFT). Both systems reside inside a 2T superconducting solenoid. Details of the Dtracking system can be found in [[1]]. The CFT consists of eight axial and eight stereo layers of scintillating fibers. Each axial and stereo layer consists of a doublet of fibers. There is full eight layer coverage for || < 1.6. The L1CFT uses hits from the eight axial layers to find tracks with PT > 1.5 GeV/c. The layers are named “A” (innermost) through “H” (outermost). The algorithm used by the L1CFT is described in [[2]]. The CFT is divided into 80 sectors and the L1CFT sends up to six tracks per sector to the L1MU. The information sent for each track is the bin (or centroid) in the “H” layer (4 bits), the offset corresponding to the difference between the track’s “A” layer bin and that for an infinite momentum track passing through the “H” layer bin (4 bits), and the sign of the offset (1 bit).

2.2Muon Detector System

The Dmuon system is shown in Figure 1. It is divided into central (CF) (|| < 1.0) and forward (EF) (1.0 < || < 2.0) regions. Each region consists of three layers that we label “A”, “B”, and “C” and each layer has three or four decks of cells. The “A” layers are inside the muon iron toroids while the “B” and “C” layers are outside them. Details of the CF and EF muon detectors may be found in their respective Technical Design Reports (TDR’s) [[3]],[[4]],[[5]].

In the CF region, muon detection consists of three layers of proportional drift tubes (PDT’s). The information sent to the L1MU from each PDT Corner Board (CB) is a 1/0 for each of the 96 or 72 PDT cells hit/not.

Covering the A layer PDT’s are a set of barrel scintillation counters called the “APHI” counters. The APHI counters have (approximately) 4.5segmentation in phi and 9 segments in z. The phi segmentation matches the CFT sector segmentation. Covering C layer PDT’s in octants 1-5 and 8 are the “Cosmic Cap” scintillation counters. Each PDT is covered by four counters in z and two counters in phi. Another set of scintillation counters called “Bottom B” covers the B layer PDT’s in octants 6 and 7. The “Bottom C” counters cover PDT’s 205, 206, 245, and 246 also in octants 6 and 7. The Bottom B counters have (roughly) 4.5segmentation in phi and one segment in z. The information sent to the L1MU from the Scintillator Front End (SFE) electronics is a 1/0 for each counter hit/not. Good scintillator hits must satisfy a time gate of approximately 25 ns which reduces accidentals such as secondaries arising from beam and target jet interactions with beamline elements.

In the EF region, muon detection consists of three layers of mini-drift tubes (MDT’s). The MDT front end electronics (MDC’s) send a 1/0 for each MDT cell hit/not to the Muon Centroid Finder (MCEN) cards. The MCEN’s find track “stubs” in each MDT layer using two out of three or three out of four deck coincidences. Each MCEN subsequently sends to the L1MU a 1/0 for each possible centroid location.

Adjacent to each layer of MDT’s is a layer of scintillation trigger counters called “Pixels”. The Pixel counters have 4.5segmentation in phi and (approximately) 0.11 segmentation in . The information sent to the L1MU from the SFE cards is a 1/0 for each counter hit/not. Good scintillator hits must satisfy a time gate of approximately 25 ns which reduces accidentals.

2.3Accelerator Timing

A review of the accelerator timing is useful. The accelerator RF clock frequency is 53 MHz and this is used as the system clock in the L1MU system. One turn in the accelerator has 1113 RF buckets giving 159 beam bunches for 132 ns bunch spacing. Each bunch crossing (BC) is tagged with an 8 bit BC number and 16 bit turn number. In colliding beam mode, there are counter-rotating beams of protons and anti-protons. The beam structure for Run II is still being discussed. One scenario has beam in all 159 bunch spaces. Another scenario has three superbunches of beam separated by three gaps. For 132 ns bunch spacing, there are 36 beam bunches per superbunch and the gap size is 2.38 s. For 396 ns bunch spacing, there are 12 beam bunches per superbunch and the gap size is 2.64 s. The total time for a turn is approximately 21 s. The L1MU system is designed to operate under both scenarios.

One of the crossings is designated as the First Crossing. If the beam structure contains superbunches and gaps, one of the gaps is designated as the Sync Gap. If all bunch spaces are used, a Sync Gap is created by the Trigger Framework when necessary. First Crossing occurs during the Sync Gap and indicates that the first real beam crossing will occur six crossings later. That is, if the BC number associated with the First Crossing is one, the BC number associated with the first real beam crossing is seven. All timing signals (such as First Crossing) arrive at front end and trigger cards before their actual occurrence in the accelerator.

2.4Level 1 Muon Trigger

A block diagram of the L1MU system is shown in Figure 2. There are three custom VME crates of muon trigger cards corresponding to the central (CF), north (EFN), and south (EFS) geographic regions of the D detector. The VME crates reside on the detector platform and are thus inaccessible during data-taking.

Cables / Bits / Cable / Definition / Source
10 (12?) / 6 tracks x 9 bits / track / L1CFT tracks / L1CFT
2 / 45 / Aphi counter hits / Scintillator Front End Cards (SFE)
1 / 80 / Cosmic Cap counter hits / MCEN (MFO flavor)

Table 1. CF MTC05 inputs for octants 1-5 and 8.

Cables / Bits/Cable / Definition / Source
10 (12?) / 6 tracks x 9 bits / track / L1CFT tracks / L1CFT
1 / 45 / Aphi counter hits / SFE
2 / 20 x 2 and 4 + 16 = 20 / Bottom B counter hits / SFE
1 / 18 / Bottom C counter hits / SFE

Table 2. CF MTC05 inputs for octants 6 and 7.

Cables / Bits / Cable / Definition / Source
3 / 96 / A layer PDT hits / Control Board (CB)
5 / 72 / B layer PDT hits / CB
5 / 72 / C layer PDT hits / CB
2 / 45 / Aphi counter hits / SFE
1 / 80 / Cosmic Cap counter hits / MCEN (MFO)

Table 3. CF MTC10 inputs for octants 1-5 and 8.

Cables / Bits / Cable / Definition / Source
3 / 72 / A layer PDT hits / CB
4 / 72 / B Layer PDT hits / CB
4 / 72 / C Layer PDT hits / CB
1 / 45 / Aphi counter hits / SFE
2 / 20 x 2 , 4 + 16 = 20 / Bottom B counter hits / SFE
1 / 18 / Bottom C counter hits / SFE

Table 4. CF MTC10 inputs for octants 6 and 7.

Cables / Bits / Cable / Definition / Source
10 (12?) / 6 tracks x 9 bits / track / L1CFT tracks / L1CFT
2 / 48 / A Pixel counters / SFE
2 / 48 / B Pixel counters / SFE
1 / 96 / C Pixel counters / MCEN (MFO)

Table 5. EF MTC05 inputs.

Cables / Bits / Cable / Definition / Source
3 / 96 / A MDT centroids / MCEN
4 / 96 / B MDT centroids / MCEN
4 / 96 / C MDT centroids / MCEN
2 / 48 / A Pixel counters / SFE
2 / 48 / B Pixel counters / SFE
1 / 96 / C Pixel counters / MCEN (MFO)

Table 6. EF MTC10 inputs.

Bit / Definition
0 / 2 bit counter pt1, sign 0 (tight)
1 / “
2 / 2 bit counter pt1, sign 1 (tight)
3 / “
4 / 2 bit counter pt2 (tight)
5 / “
6 / 2 bit counter pt3 (tight)
7 / “
8 / 2 bit counter pt4 (tight)
9 / “
10 / 2 bit counter pt4 (loose)
11 / “
12 / 2 bit counter pt2 (loose)
13 / “
14 / 2 bit counter pt3 (loose)
15 / “

Table 7. Definition of CF MTC05 bits sent to MTCM

Bit / Definition
0 / 2 bit counter pt1, sign 0 (tight)
1 / “
2 / 2 bit counter pt1, sign 1 (tight)
3 / “
4 / 2 bit counter pt2 (tight)
5 / “
6 / 2 bit counter pt3 (tight)
7 / “
8 / 2 bit counter pt4 (tight)
9 / “
10 / 2 bit counter pt4 (loose)
11 / “
12 / 2 bit counter pt1, no L1CFT region
13 / “
14 / 2 bit counter pt2, no L1CFT region
15 / “

Table 8. Definition of EF MTC05 bits sent to MTCM

Bit / Definition
0 / 2 bit counter PDT A centroid
1 / “
2 / 2 bit counter PDT AB or AC Centroid
3 / “
4 / 2 bit counter PDT AB or AC or BC Centroid
5 / “
6 / Spare
7 / “

Table 9. Definition of CF MTC10 bits sent to MTCM

Bit / Definition
0 / 2 bit counter, MDT A centroid (L1CFT region)
1 / “
2 / 2 bit counter, MDT AB or ABC centroid (L1CFT region)
3 / “
4 / 2 bit counter, MDT A centroid (no L1CFT region)
5 / “
6 / 2 bit counter, MDT AB or ABC centroid (no L1CFT region)
7 / “

Table 10. Definition of EF MTC10 bits sent to MTCM

BYTE # / Definition
1 / Start of Transmission
2 / Crate Trigger Decision Byte 1
3 / Crate Trigger Decision Byte 2
4 / MTCM Error Byte 1
5 / MTCM Error Byte 2
6 / Unassigned
7 / Parity

Table 11. MTCM Inputs to MTM

Byte.BIT / Description
1.0 / 2 bit counter pt1, sign0 (tight)
1.1 / “
1.2 / 2 bit counter pt1, sign1 (tight)
1.3 / “
1.4 / 2 bit counter for pt2 (tight)
1.5 / “
1.6 / 2 bit counter for pt3 (tight)
1.7 / “
2.0 / 2 bit counter for pt4 (tight)
2.1 / “
2.2 / 2 bit counter for pt4 (loose)
2.3 / “
2.4 / 2 bit counter for pt1 (no L1CFT trigger)
2.5 / “
2.6 / 2 bit counter for pt2 (no L1 CFT trigger)
2.7 / “

Table 12. Definition of MTCM regional trigger bits sent to the MTM

Byte # / Description
1 / Begin of File Character
2 - 3 / Global Data Length (without Nulls)
5 - 6 / Block data Length (without Nulls)
7 - 8 / Turn (Rotation) Number
9 - 10 / Spare
11 - 12 / Bunch Crossing Number
13 - 14 / Crate Trigger Decision Bytes
15 - 46 / Card Trigger Data
47 - 78 / Supplemental Card Trigger Data
79 - 80 / MTCM Error Bytes
80 - 81 / MTCM Status Bytes
82 / Parity
83 / End of File Character

Table 13. Definition of data sent from the MTCM to L2MU

Byte # / Description
1 / Begin of File Character
2 - 3 / Global Data Length (without Nulls)
3 - 4 / Block data Length (without Nulls)
5 - 6 / Turn (Rotation) Number
7 - 8 / Bunch Crossing Number
9 - 10 / Spare
11 - 522 / Header Information containing FPGA Program I.D.s and mask registers
523 - 524 / Crate Trigger Decision Bytes
525 - 556 / Card Trigger Data
557 - 588 / Supplemental Card Trigger Data
589 - 590 / MTCM Error Bytes
591 - 592 / MTCM Status Bytes
593 - 652 / MTCxx Status/Error Bytes
653 - 654 / Block data Length (without Nulls)
655 - 3726 / Raw Data from MTCxxs (192 bytes/card) (when this crossing is 1 of n)
3727 / Parity
3728 / End of File Character

Table 14. Definition of data sent from the MTCM to L3 via the MRC

Pair / Definition
1 / trigger term 0
2 / trigger term 1
3 / trigger term 2
4 / trigger term 3
5 / trigger term 4
6 / trigger term 5
7 / trigger term 6
8 / trigger term 7
9 / trigger term 8
10 / trigger term 9
11 / trigger term 10
12 / trigger term 11
13 / trigger term 12
14 / trigger term 13
15 / trigger term 14
16 / trigger term 15
17 / gap
18 / ground
19 / strobe
20 / ground

Table 15. Definition of MTM trigger bits and signals sent to the Trigger Framework

The MTCxx trigger logic is implemented in Altera FLEX 10K series FPGA’s. The FPGA logic is stored in non-volatile RAM on each card for easy reprogramming after power cycling. The trigger logic is described in more detail in the Muon Trigger Flavor Board (MTFB) section however a very brief description is provided here for completeness. The basic trigger logic is combinatorial. The CF MTC05 logic matches the “H” centroids of L1CFT tracks with Aphi counter hits for low PT muons and with Aphi counter hits and Cosmic Cap counter hits for high PT muons. Similarly, the EF MTC05 logic matches the “H” centroids of L1CFT tracks with A layer Pixel counter hits for low PT muons and with three layers (A, B, C) of Pixel counter hits for high PT muons. The CF MTC10 logic first finds centroids (stubs) based on hit patterns in the PDT’s. These centroids are next “confirmed” by an appropriate Aphi, Bottom B, or Cosmic Cap counter hit. Low PT muon candidates are identified by a confirmed A layer centroid. High PT muon candidates are identified by requiring centroids consistent with a track in two of three layers. Because of the large channel count, centroids in the three layers of MDT’s are found on separate cards called the Muon Centroid (MCEN) cards. The EF MTC10 logic accepts these centroids and first confirms them by an appropriate A, B, or C Pixel counter hit. Low PT muon candidates are identified by a confirmed A layer centroid. High PT muon candidates are identified by requiring centroids consistent with a track in all three layers. Again, additional details on the trigger logic are spelled out in the MTFB section.

In each muon trigger VME crate resides a muon trigger crate manager (MTCM). On each live beam crossing, the MTCM reads sixteen (eight) bits of octant trigger decision information from each MTC05 (MTC10) card in the crate over the custom J2 backplane. The octant trigger decision information is typically two bit counters for different PT thresholds, regions, or trigger qualities. This information is used by the MTCM to form a sixteen bit regional trigger decision. The regional trigger decision from each MTCM card is sent to the muon trigger manager (MTM) over coaxial cable using a high speed serial link. The MTM is really an MTCxx card with an MTM flavor daughter board. The MTM uses these regional trigger decisions along with information downloaded from the online data acquisition (DAQ) program to send sixteen global muon trigger states to the trigger framework for inclusion in the L1 global physics trigger decision. Communication with the muon trigger crate, FPGA program downloading, and error monitoring are performed via a MIL-STD-1553B interface on the MTCM.