Computer Applications and Management

A-4, Paschim Vihar, New Delhi-63.

MCA – 2nd Semester (2009-12)

IInd Internal Test Computer System Architecture – MCA - 106

Max. Marks: 45 Max. Time: 03 Hrs.

SECTION-A

Q1. Answer any TEN of the following: (1.5*10=15)

  1. What do you understand by traps?
  2. What must be the address field of an indexed addressing mode instruction be to make it the same as register indirect mode instruction?
  3. What is a task?
  4. What do you understand by memory interleaving?
  5. What are the basic components of memory management unit?
  6. Why does DMA have priority over the CPU when both request a memory transfer?
  7. Name three different modes in which data can transmitted between two different points.
  8. A non-pipeline system takes 50 ns to process a task. The same task can be processed in six segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum speedup that can be achieved?
  9. How many characters per second can be transmitted over a 1200-baud line in synchronous serial transmission?
  10. What is the basic difference between a branch instruction, a call subroutine instruction, and a program interrupt?
  11. A computer uses RAM chips of 1024*1 capacity. How many chips are needed to provide memory capacity 16K bytes?
  12. What is the difference between address and memory space?
  13. A digital computer has a memory unit of 64 K * 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words. How many bits are there in tag, index, block and word fields of the address format?

SECTION-B

Attempt any three of the following:

Q2.

a. An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is

  1. Direct
  2. Immediate
  3. Relative
  4. Register indirect
  5. Index with R1 as the index register. (5)

b. Explain four possible hardware schemes that can be used in an instruction pipeline in order

to minimize the performance degradation caused by instruction branching. (5)

Q3.

a.  Explain Booth’s algorithm for multiplication of signed -2’s complement numbers. Give the schematic diagram of the hardware needed to implement Booth’s algorithm. Depict the algorithm using the hardware through a flow chart’s what happens when there is an overflow? (5)

  1. Explain in details Daisy Chain priority interrupt Scheme. (5)

Q4.

  1. A commercial interface unit uses different names for the handshake lines associated with the transfer input handshake lines associated with the transfer of data from the I/O device into the interface unit. The interface unit handshake line is labeled STB
    (strobe), and the interface output handshake line is labeled IBF( input buffer full). A low-level signal on STB loads data from the I/O bus into the interface data register. A full high-level signal on IBF indicates that the data item has been accepted by the interface. IBF goes low after an I/O read signal from the CPU when it reads the contents of the data register.

i.  Draw a block diagram showing the CPU, the interface, and the I/O device together withy the pertinent interconnection among the three units (2)

ii.  Draw a timing diagram for the handshaking transfer (2)

iii.  Obtain a sequence-of-events flowchart for the device to the interface and

from the interface to the CPU. (3)

b.  What is the difference between isolated I/O and memory mapped I/O? What are the advantages and disadvantages of each? (3)

Q5.

  1. What is mapping? Discuss three different types of mapping procedures? (7)
  1. Construct a diagram for a 4*4 omega switching network. Show the switch setting required to connect input 3 to output 1 (3)

Q6.

  1. Discuss different schemes for establishing an interconnection network. (7)
  1. An address space is specified by 24-bits and the corresponding memory space by 16-bits.

i.  How many words are there in the address?

ii.  How many words are there in memory space?

iii.  If a page consist of 2K words, how many pages and blocks are there in the system?

(3)