BACHELOR DEGREE IN TELECOMMUNICATIONS / Digital Circuits and Systems (CSD)
3GT31-3GT32 / 10/01/2012

-Third individual test. Grades will be available on Friday, 13 Januaryth.

-Questions about the exam: Monday 15:00-17:00; Friday 14:30-16:30.

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1-This is a block diagram corresponding to the serial receiver of the UART.[4P]

a)Indicate the modules corresponding to the datapath. Justify your response.

b)Indicate the way that how you would obtain Rx_CLK from a clock source of 25.175 MHz. If Serial-in comes at 110 bit/s, which what is the value of Rx_CLK?

c)Explain how and when New_data output is generated.

d)If you see identify any mistake or anymissing component in this block diagram, indicate how you would you solve it.

2-Explain in general the function of the Control Unit and the Operational Unit of the following block diagram. Indicate the blocks included in the Control Unit and in the Operational Unit. Indicate the control lines and the status lines involved. If TX_CLK is 9600 Hz, indicate the duration of ET. [4P]

3-Draw the state diagram corresponding to the following VHDL code.[2p]

------CC1: Combinational system for calculating next state
CC_1: PROCESS (present_state, TRIG, TC)
BEGIN
-- just a simple state up count
CASE present_state IS
WHEN Idle1 =>
IF TRIG = '0' THEN
future_state <= Idle1 ;
ELSE
future_state <= Clear1 ;
END IF;
WHEN Clear1 =>
future_state <= Count1 ;
WHEN Count1 =>
IF TC = '0' THEN
future_state <= Count1 ;
ELSE
future_state <= Idle1 ;
END IF;
END CASE ;
END PROCESS CC_1;
------CS_2: combinational system for calculating extra outputs
------and outputingoutputting the present state
CC_2: PROCESS (present_state)
BEGIN
-- And now just copying the present state to the output:
CASE present_state IS
WHEN Idle1 =>
ENABLE <= '0';
CLEAR <= '0';
WHEN Clear1 =>
CLEAR <= '1';
WHEN Count1 =>
ENABLE <= '1';
CLEAR <= '0';
END CASE ;
END PROCESS CC_2;