A

Summer Training Report

Radha Govind Research Centre For

Microelectronics & InfoTech

On

Digital Clock

Based on V.H.D.L

Submitted by Guided by

Gaurav Suman Mr. Kamlesh Kumar

B.tech 3rd year Mr. Ramesh Kumar

Branch-E.C Mr. Deependra Panday

Roll No.-0206931026 Mr. Sanjay Viswkarma

Submitted To

Radha Govind Engineering College

Contents

  1. Acknowledgement
  2. About RGRMI
  3. Introduction to VHDL
  4. Overview of VHDL
  5. History of VHDL
  6. Building blocks of VHDL
  7. Data type and operator
  8. VHDL Constructs
  9. Design Units of VHDL
  10. Introduction of Digital clock
  11. Block Diagram
  12. Flow Chart
  13. VHDL Code For Digital Clock
  14. Waveform
  15. Synthesis
  16. FPGA
  17. Bibliography

acknowledgement

An endeavor over a long period can be successful only with the advice & guidance of many well wishers .I take this opportunity to express my deep gratitude and appreciation to all those who encourage us to successfully complete the project.

First and foremost, I would like to thank my internal guides Mr. KAMLESH KUMAR SINGH and Mr. RAMESH KUMAR with out whom the project would have been a dream.

I take this opportunity to express my indebtedness to Mr. DEEPENDRA PANDEY and Mr. SANJAY VISHWKARMA.

I would like to express my sincere gratitude to my FRIENDS specially Mr. Prateek Pathak, Mrs. Archana, Mr. Mukesh & Miss Mini for timely help & support.

GAURAV SUMAN

ABOUT RGRMI

(RADHA GOVIND RESEARCH CENTRE FOR MICROELECTRONICS & INFOTECH)

RGRMI is providing high-end training & services to the corporate & individuals in the various fields of most modern technologies. It also provides complete software & web solutions with state-of-art infrastructure & trainers; RGRMI is able to make a niche for itself in the field of training.

RGRMI is a pace maker in the various demanding sectors, as a market radar it trace the new trends & technologies in the industry very early on & develop training roadmap at very early stage.

At RGRMI, complete team of highly qualified adept hardware, software & network engineers full of vigor & strive to design training programs to meet the needs of individuals & organizations by incorporating the latest technologies in its training modules & ensuring that the best of trainers are available to deliver the same.

Introduction to VHDL

VHDL is an acronym for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language which is a programming language that describes a logic circuit by function, data flow behavior, and/or structure. This hardware description is used to configure a programmable logic device (PLD), such as a field programmable gate array (FPGA), with a custom logic design. The general format of a VHDL program is built around the concept of BLOCKSthat are the basic building units of a VHDL design. Within these design blocks a logic circuit of function can be easily described. A VHDL design begins with an ENTITYblock that describes the interface for the design. The interface defines the input and output logic signals of the circuit being designed. The ARCHITECTURE block describes the internal operation of the design. Within these blocks are numerous other functional blocks used to build the design elements of the logic circuit being created.

After the design is created, it can be simulated and synthesized to check its logical operation. SIMULATION is a barebones type of test to see if the basic logic works according to the design and its concepts. SYNTHESIS allows the timing factors and other influences of the actual field programmable gate array (FPGA) devices to effect the simulation thereby doing a more thorough type of check before the design is committed to the FPGA or a similar device.

Many software packages used for VHDL design also support schematic capture which takes a logic schematic or state diagram and translates it into the VHDL code. This, in turn, makes the design process a lot easier.

Overview of VHDL

VHDL stands for VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit. It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between.

VHDL can be regarded as an integrated amalgamation of the following languages:

Sequential + Concurrent + Net List + Timing Specification + Simulation+ Test Language

Therefore the language has constructs that enable to express the concurrent or sequential behavior of a digital system with or without timing. It also allows modeling the system as an interconnection of components. Test waveforms can also be generated using the same constructs. All the above constructs can be combined to provide a comprehensive description of the system in a single model.

History of VHDL

The requirements for the VHDL language were generated in 1981 under the VHSIC program. In this program a number of companies involved in designing VHSIC chips for the Department of Defence (DoD). At that time, most of the companies were using different hardware description languages to describe and develop their integrated circuits. As a result, different vendors could not effectively exchange their design with one other.

A team of three companies IBM, Texas Instruments and Intermetrics were first awarded the contract by the DoD to develop a version of language in 1983. Version 7.2 of VHDL was developed and released to public in 1985.

After substantial enhancements to the language, made by a team of industry, University and DoD representatives, the language was standardized by IEEE in December 1987. This version of language is known as the IEEE STD 1076-1987. The language has also been recognized as an American National Standard Institute (ANSI) Standard.

Since 1987, there was a great need for a standard package to aid in model interoperability. This was because different CAE (Computer Aided Engineering) vendors supported different package on their systems, causing major model interoperability problems. Some of the logic values used were 46-value logic, 7-value logic, 4-value logic, and so on. A committee was set up to standardize the logic package. The outcome of this committee was the development of a 9-value logic package. This package, called STD_LOGIC_1164, was then balloted and approved to become IEEE standard, labeled IEEE STD 1164-1993.

Advantages of VHDL over other Hardware Description

Languages:

1. The language can be used as a communication medium between different CAD and CAE tools.

2. The language supports hierarchy; that is, a digital system can be modeled as a set of interconnected components and each component in turn can be modeled as a set of interconnected subcomponents.

3. The language supports flexible design methodologies: top down bottom-up or mixed.

4. It supports both synchronous and asynchronous timing models.

5. Various digital modeling techniques such as Finite State Machine descriptions, algorithmic descriptions and Boolean equations can be modeled using this language.

6. The language is publicly available, human readable, machine readable and not proprietary.

7. The language supports three basic different description styles: Structural, Dataflow and Behavioral.

8. Arbitrarily large designs can be modeled using the language and there are no

Limitations imposed by the language on the size of a design.

9. The model can not only describe the functionality of a design, but also contain information about the design itself in terms of user-defined attributes, such as total area and speed.

10. The capability of defining new data types provides the power to describe and simulate a new design technology at a very high level of abstraction without any concern about the implementation details.

Features of VHDL

  • The language has powerful constructs like if then else, with select.
  • Supports Design hierarchies to create modular design.
  • It supports design libraries.
  • It facilitates device independent design and portability.
  • it provides modular designing and testing
  • Use of VHDL reduces the time-to-market for large and small designs.

VHDL is amalgamation of the following languages:

  1. Concurrent language
  2. Sequential language
  3. Netlist language
  4. Timing language
  5. Simulation language
  6. Test language

Building blocks of VHDL

VHDL is a Hardware Description Language that can be used to model a digital system. The digital system can be as simple as a logic gate or as complex as a complete electronic system. The building blocks of this language are known as design units.

The five main design units under VHDL are:

1. Entity declaration.

2. Architecture declaration.

3. Configuration declaration.

4. Package.

5. Library.

1.Entity declaration: The entity declaration describes the external view of an entity. The entity declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals (wires) through which the entity communicates with the other models in its external environment.

2.Architecture declaration: An architecture declaration is a statement that describes the underlying function and/or structure of a circuit.Every entity declaration must be accompanied by at least one corresponding architecture.

3.Configuration declaration: A configuration declaration is used to select one of possibly many architecture bodies that an entities may have, and to bind components used to represent structure in that architecture body.

4.Package:A package is a common storage area used to hold data to be shared among a number of entities. Declaring data inside of a package allows the data to be referenced by other entities; thus, the data can be shared. There are some predefined packages like IEEE.STD_LOGIC_1164.all which have standard logic, data type, logical functions and subprograms.

5.Libraries: library is the collection of all compiled units, packages and configurations. Every VHDL compiler has at least three libraries:

a. IEEE STD_LOGIC_1164.all

b. STD Standard functions

c. WORK Default library( for all the compiled

program)

Data types and Operators

Language elements:

  • Identifiers
  • Literals
  • Data type (Bit, Bit_Vector, Std_Logic, Integer etc.)
  • Operators (Arithmetical, Logical, rotational and shift etc.)
  • Object types (Signal , Variable, Constant and File)

Identifiers

  1. Can consist of a certain number letters and underscore.
  2. Must begin with a letter.
  3. Case Insensitive.
  4. The first letter should be a character and last should not be an underscore.
  5. Reserved word (keyword) should not be used.
  6. No space is allowed.
  7. The Max. Length should be 16.
  8. For more than 16, we can use underscore. E.g.: character_literals.

Literals

Numerical literal: It contains Numbers. E.g.: 0, 1, 2, 3... 9

Character literal: Character and string both is used.

E.g.: ‘A’ ………………’Z’ & ‘a’………….’z’

String

E.g.: “word”

Bit literals: 1. It is used to represent the value of digital system.

2. Bit vector is expressed as a string of literal.

Example: ‘1’, ‘0’, “1001”

Boolean literals: It represents true and false conditions.

E.g.: True (TRUE, true)

False (FALSE, false)

Real literals: They define a real value. They can either positive or negative but exponent is always an integer. E.g.: 3.23, -1.78, -4,23E23,

Integer literals: It defines a value with integer; E.g.: 3, -1 , -4E-2, 16#3

Data type

Std_ logic Type :

# It is a data type defined in the std_logic_1164.all package of IEEE library.

# It have a no. of states of digital signal .

# It is an enumerated type and defined as

type std_logic(‘U’,’X’,’0’,’1’,’Z’,’W’,’L’,’H’,’-‘)

U = Un Initialized , X= Forcing Un known, ‘0’= forcing 0, ‘1’ = forcing 1,

Z = high impedance, ‘W’= weak unknown, L = Weak 0, H= weak 1,

‘-‘= don’t care

U is the default value.

Enumerated type:

An enumerated type is a user defined value consisting identifiers and character literals.

Syntax:

Type enumerated_ type_ name is (enumerated literal1, literal 2);

E.g.: Type color is (red, blue, green);

Composite type:

There are two composite types:

  1. Array
  2. Record

Array: It can be either uni or multidimensional.

Assignment to an array:

A<= ( ‘1’,’0’, others=>’0’) means A <= “1000”

A<= “10” and “11”

A<=’1’&’0’&’1’&’1’

C <=A & B

Slicing :

Y<= 101110 ( 0 downto 5)

X<= Y(2 to 4) means X<= 111

Array declaration :

type array_name is array(index_range, index range) of element_type

E.g.: type arry is array ( 3 downto 0, 7 downto 0) of std_logic;

Operators and Operand

Logical Operator / AND, OR, NAND, NOR, XOR
Relational Operator / =, /=, <, <=, >, >=
Adding Operator / +, - , &,
Sign / +, -
Multiplying Operator / *, /, mod, rem
Miscellaneous Operator / **, abs, not

Object Types

There are four types of objects in VHDL

  • Signal
  • Variable
  • Constant
  • File

Signal:

Signal declarations create new signals (wires) of a given type. They can be used to communicate between processes or to synchronize processes. Signal can be declared in package declarations (global signals), entities (entity global signal), architectures (architecture global signals) & blocks. They can be used but cannot be defined in processes & subprograms. Signal latches past value. The syntax for a signal declaration is as follows:

Signal signal_name: signal_type {range}:= [initial value]

Variable:

Variables are used to hold temporary data. They don’t have past history. They can only be declared in a process or a subprogram. A variable must declare a type & can be given a range constraint or an initial value. The syntax for variable declaration is as follows:

Variable variable_name: variable_type {range}:= [initial value]

Constants:

A constant is an object, which is initialized to a specific value when it is created, & which cannot be subsequently modified. Constant declarations are allowed in packages, entities, architectures, subprograms, blocks & processes. The syntax for a constant declaration is:

Constant constant_name : type_name [:=value] ;

Constructs

VHDL Constructs

Concurrent Constructs Sequential Constructs

Data flow modeling Behavioral modeling

  1. Signal declaration 1. If then else
  2. When else statement 2. Case statement
  3. With select statement 3. Loop statement
  4. Block statement 4. Exit statement
  5. Generate statement 5. Null statement
  6. Component statement 6. Next statement
  7. process statement

Sequential Statement

  • Used in process and Subprograms.
  • Order of execution is the order in which statement written

Concurrent Statement

  • Order of statements does not matter.
  • Statements are executed only when triggered.

Additional Features of Concurrent Statement:

  • Execute simultaneously
  • Use to express parallel activity in case of digital circuit.
  • Concurrent statements dot executes with any predefined order.
  • It can be used for data behavioral and structure
  • In side of process statement, only sequential statements are allowed.

Design Units of VHDL:

To describe an entity, VHDL provides five different types of primary constructs, called design units. They are:

  1. Entity declaration
  2. Architecture body
  3. Configuration declaration
  4. Package declaration
  5. Package body

An entity is modeled using an entity declaration and at least one architecture body. The entity declaration describes the external view of the entity; for example, the input and output signal names.

The architecture body contains the internal description of the entity; for example, as a set of interconnected components that represents the structure of the entity, or as a set of concurrent or sequential statements that represent the behavior of the entity. Each style of representation can be specified in a different architecture body or mixed within a single architecture body.

A configuration declaration is used to create a configuration for an entity. It specifies the binding of one architecture body from the many architecture bodies that may be associated with the entity it may also specify the bindings of components used in the selected architecture body to other entities. An entity may have any number of different configurations.

A package declaration encapsulates a set of related declaration, such as type declaration, subtype declarations, and subprogram declarations, which can be shared across two or more design units. A package body contains the definitions of subprograms declared in a package declaration.

Entity Block:

The entity block is the building block of a VHDL design. Each design has only one entity block which describes the interface signals IN and OUT of the design unit. The syntax for an entity is as follows:

entity entity_name is

port (signal_name 1, signal_name 2 : mode type ;

signal_name 3, signal_name 4 : mode type ) ;

end entity_name;

In general there are three frequently used modes i.e. in, out and inout setting the signal flow direction for the ports as input, output and bi-directional. Signal declarations of different mode or type are listed individually and separated by semicolons. A semicolon on the outside of the port’s closing parenthesis terminates the last signal declaration in a port statement itself.

EXAMPLE:

Here is an example of an entity declaration for the half adder circuit as shown in the figure given below:

entity HALF_ADDER is

port (A, B : in BIT;

SUM, CARRY : out BIT);

end HALF_ADDER;

Architecture Body:

The internal details of an entity are specified by an architecture body using any of the following modeling styles:

  1. As a set of interconnected components (to represent the structure)
  2. As a set of concurrent assignment statements (to represent data flow)
  3. As a set of sequential assignment statements (to represent behavior)
  4. A combination of any of the above.

A general syntax for the architecture block is as follows:

architecture arch_name of entity_name is

declarations;

begin

statements defining operation;

end arch_name;

Structural Style of Modeling:

In the structural style of modeling the entity described as a set of interconnected components. The declared components are instantiated in the statement part of the architecture body using the component instantiation statements. A component instantiation statement is a concurrent statement. Therefore, the order of the statement is not important. The structural style of modeling describes only an interconnection of the components (viewed as black boxes), without implying any behavior of the components themselves nor of the entity that they collectively represent.

EXAMPLE:

A structural style of modeling for a half adder, as shown in the figure given below, is explained:

architecture HA_STRUCTURE of HALF_ADDER is

component XOR2

port (X,Y: in BIT;

Z: out BIT);

end component;

component AND2

port (L,M: in BIT;

N: out BIT);

end component;

begin

X1: XOR2 port map (A, B, SUM);

A1: AND2 port map (A, B, CARRY);

end HA_STRUCTURE;

Dataflow Style of modeling:

In this modeling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified in this modeling style, but it can be implicitly deduced. The dataflow model for any entity is described using two concurrent signal assignment statements. In a signal assignment statement, the symbol <= implies an assignment of a value to a signal. The value of the expression to the right hand side of the statement is computed and assigned to the signal on the left hand side, called the target signal. A concurrent signal assignment statement is executed only when any signal used in the expression on the right hand side has an event on it, that is, the value for the signal changes.