Low-Power and Area-Efficient Carry Select Adder

WYV61

Ramkumar, B.

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:20 , Issue: 2 )

DOI: 10.1109/TVLSI.2010.2101621

Publication Year: 2012 Page(s) : 371 – 375

Project Title : Low-Power and Area-Efficient Carry Select Adder

Domain : VLSI

Reference : IEEE

Publish Year : 22-23 Feb. 2013 Page(s): 1656 – 1663

D.O.I 10.1109/TVLSI.2010.2101621

Software Tool : XILINX

Language : Verilog HDL

Developed By : Wine Yard Technologies, Hyderabad

Low-Power and Area-Efficient Carry Select Adder

Abstract:

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level of abstraction. It is also used in the verification of analog and mixed-signal circuits.Provides an overview of the Xilinx Integrated Software Environment (ISE), including design flow information .Explains how to create, define, and compile your FPGA or CPLD design using the suite of ISE tools available from the Project Navigator. Describes what’s new in the software release and how to migrate past projects to the current software

Existing method:

Anadderorsummeris adigital circuitthat performsadditionof numbers. In manycomputersand other kinds of processors, adders are used not only in thearithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations. Although adders can be constructed for

many numerical representations, such asbinary-coded decimalorexcess-3, the most common adders operate onbinarynumbers. In cases where two's complementorones' complementis being used to represent negative numbers, it is trivial to modify an adder into anadder–subtractor. Othersigned number representationsrequire a more complex adder.

Existing more complex adders:

1. Ripple-carry adder

2. Look ahead carry unit

3. Carry-save adders

4. Carry-skip adders

5. Carry-select adders using dual RCA’s

Proposed method:

The development in the field of nanometer technology leads to minimize the power consumption of logic circuits. More complex Adders (carry select adder) using Binary to Excess (BEC’s) design has been one of the promising technologies gaining greater interest due to less dissipation of heat, less area and low power consumption. In the digital design, the adder is a widely used process. So, carry select adder design using Binary to Excess design has been proposed, the adders like 4bit,8bit,16bit using conventional logic gates is proposed. The proposed design leads to the reduction of delay, area, power consumption are compared with existing techniques.

Applications:

1. Digital systems designing

2. Digital signal processing

3. Multiplication

4. Arithmetic and Logic Unit (ALU)

5. Microprocessors

Advantageous:

1. Area Efficient adders.

2. Low power adders.

3. High speed adders.

Conclusion:

A simple approach is proposed in this paper to reduce the area and power of SQRT CSLA architecture. The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power. The compared results show that the modiﬁed SQRT CSLA has a slightly larger delay (only 3.76%), but the area and power of the 64-b modiﬁed SQRT CSLA are signiﬁcantly reduced by 17.4% and 15.4% respectively. The power-delay product and also the area-delay product of the proposed design show a decrease for 16-, 32-, and 64-b sizes which indicates the success of the method and not a mere tradeoff of delay for power and area. The modiﬁed CSLA architecture is therefore, low area, low power, simple and efﬁcient for VLSI hardware implementation. It would be interesting to test the design of the modiﬁed 128-b SQRT CSLA.

Circuit Diagram:

Screen shots:

RCA:

CSLA(BEC’S):