JOB DESCRIPTION

Position Title: Digital Algorithm / Design Engineer

Department:

RF Lab

Job Description:

Developing digital baseband for MMMB wireless handset:

  • digital filtering
  • digital up conversion
  • digital gain control
  • digital calibrations

Developing digital RF transceiver

Developing digital RFIC

Requirements:

  • Doctor of Philosophy (Ph.D.) or Master of Sciences (MS) Degree
  • Knowledge of concept of multi-rate signal processing and digital IF algorithm
  • Experience in high speed digital circuit design

Required Skills and Experience:

  • Experience in DSP algorithm and high speed digital design
  • Expertise in Verilog development languages
  • Experience in digital ASIC design
  • Knowledge of wireless communication standards (EDGE/HSPA/LTE)

Essential Job Functions:

  • Implementing digital baseband algorithm using Verilog development language
  • Developing high-speed digital design for FPGA/ASIC
  • Developing calibration algorithm such as IQ mismatch and DC offset group delay compensation

In order to apply, please, fill out and send us the Standard Samsung Electronics Curriculum Vitae (CV) in English at the email: (with the subject line of your email: Professional Resume)

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Position Title: ADC / PLL Designer

Department:

RF Lab

Job Description:

  • Wideband high resolution ADC required for advanced communication standards such as LTE and LTE-ADV
  • Low jitter PLL design for high speed ADC and Digital Logic
  • Designing ADC or PLL for advanced communication standards

Requirements:

  • Doctor of Philosophy (Ph.D.) or Master of Sciences (MS) Degree
  • Familiarity with cadence analog circuit tools
  • Experience in Pipeline / Delta-Sigma ADC
  • PLL Experience

Essential Job Functions:

  • ADC spec generation required for advanced communication standards
  • Specs for components for Pipeline / Delta-Sigma ADC
  • Circuit level simulation / Layout
  • ADC chip test

In order to apply, please, fill out and send us the Standard Samsung Electronics Curriculum Vitae (CV)in English at the email: (with the subject line of your email: Professional Resume)

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Position Title: Senior Power Management Design Engineer

Department:

SoC Platform Team, RF Lab.

Job Description:

  • Developing a multi-channel power management IC (PMIC) for mobile phones
  • Switching DC-DC converters (Buck/Boost), low drop-out linear regulators (LDO), white LED driver, and Li-ion battery charger
  • Strong analog IC design background as well as power IC one, such as OP amp design

Required Skills & Experience:

  • Doctor of Philosophy (Ph.D.) or Master of Sciences (MS) Degree
  • Experience in designing core blocks (such as the switching DC-DC converter, buck, boost, pulse width modulator (PWM), pulse frequency modulator (PFM), light load mode, low drop-out linear regulators (LDO), charge pump, Boost white LED driver, Li-ion battery charger, power path, bandgap reference, operational amplifier (op amp), stability compensation, soft start)
  • CAD tools (such as Cadence schematic design, simulation and layout); DRC and LVS skills
  • Fluent in English (knowledge of Korean is a plus)
  • Ability to set up one’s own design project from beginning to the end: architecture design, block design, top integration and chip layout
  • Ability to generate data sheet, test procedure, and white paper in an efficient manner
  • Ability to work in a team project environment: cooperating with other engineers, reporting to the project lead, and mentoring the junior engineers

Essential Job Functions:

  • Switching DC-DC converter design PWM/PFM
  • Battery charger IC design
  • Power path, under-voltage lock-out (UVLO)
  • LED driver IC design
  • Class-D audio amplifier design
  • Operational amplifier (op amp) design
  • Compensation
  • Analog integrated circuit (IC) design
  • CMOS/BiCMOS/BCD

In order to apply, please, fill out and send us the Standard Samsung Electronics Curriculum Vitae (CV) in English at the email: (with the subject line of your email: Professional Resume)

WWW:

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