CSE 670: Spring 2002 Richard E. Haskell
Lab 4 – A VHDL ROM
By adding an instruction ROM and simple program counter to Lab 3, the small single-cycle processor shown in Figure 1 can be implemented.
Figure 1 A single-cycle processor
Part A:
A 4-bit up counter can be used as a simple program counter to address the instruction ROM. Listing 1 and 2 shows the entity and architecture for a 4-bit up counter, respectively.
-- A 4-bit up-counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity Tcount is
port (
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (3 downto 0)
);
end Tcount;
Listing 1 Entity for Tcount.vhd
architecture Tcount_arch of Tcount is
begin
process (clk, clr)
variable COUNT: STD_LOGIC_VECTOR (3 downto 0);
begin
if clr = '1' then
q <= "0000";
elsif clk'event and clk='1' then
COUNT := COUNT + 1;
q <= COUNT;
end if;
end process;
end Tcount_arch;
Listing 2 Architecture for Tcount.vhd
In addition to a standard ROM, it is useful to define constant instruction words to use in the ROM in place of the hex opcodes. Listing 3 shows the VHDL code for the instruction ROM with the instruction words.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity Trom is
port (
addr: in STD_LOGIC_VECTOR (3 downto 0);
M: out STD_LOGIC_VECTOR (4 downto 0)
);
end Trom;
architecture Trom_arch of Trom is
constant SWpush: STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant plus: STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant oneplus: STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant invert: STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant twotimes: STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant dup: STD_LOGIC_VECTOR (4 downto 0) := "10000";
subtype rom_word is std_logic_vector(4 downto 0);
type rom_array is array (0 to 7) of rom_word);
constant rom: rom_array := (
SWpush, SWpush,
plus, twotimes,
DUP, invert,
oneplus, plus
);
begin
process(addr)
variable j: integer;
begin
j := conv_integer(addr);
M <= rom(j);
end process;
end Trom_arch;
Listing 3 Trom.vhd
For convenience, microcoded instructions were used for this simple single-cycle processor. Figure 2 shows the instruction format using the signals nload, tload, msel, and alusel.
Figure 2 Single-cycle microcoded instructions
Listing 4 shows the top-level design, T5main.vhd, for the single-cycle processor.
library IEEE;
use IEEE.std_logic_1164.all;
entity T5main is
port (
SW: in STD_LOGIC_VECTOR (1 to 8);
BTN: in STD_LOGIC_VECTOR (1 to 4);
LD: out STD_LOGIC_VECTOR (1 to 8);
AtoG: out STD_LOGIC_VECTOR (6 downto 0);
A: out STD_LOGIC_VECTOR (3 downto 0)
);
end T5main;
architecture T5main_arch of T5main is
signal tin, T, N, y: std_logic_vector(7 downto 0);
signal P: std_logic_vector(3 downto 0);
signal M: std_logic_vector(4 downto 0);
signal clr, clk: std_logic;
begin
U0: mux2 port map
(a =>SW, b => y, sel => M(2), y => tin);
Treg: reg port map
(d => tin, load =>M(3), clr => clr, clk =>clk, q => T);
Nreg: reg port map
(d => T, load => M(4), clr => clr, clk =>clk, q => N);
U1: alu port map
(a => T, b => N, sel => M(1 downto 0), y => y);
U2: step_display port map
(dig1 => T(3 downto 0), dig2 => T(7 downto 4),
dig3 => N(3 downto 0), dig4 => N(7 downto 4), step => BTN(4),
clr => BTN(1), clkout => clk, clrout => clr,
A => A, AtoG => AtoG);
U3: Tcount port map
(clr => clr, clk => clk, q => P);
U4: Trom port map
(addr => P, M => M);
LD <= SW;
end T5main_arch;
Listing 4 T5main.vhd
Synthesize and implement this program for the Spartan2 FPGA and download the program to the Spartan2-DIO1 board. First, press and release BTN1 to clear the single-cycle processor, then use BTN4 to single-step through the program. Explain each instruction.
Part B:
Modify the circuit by making the data busses 16 bits wide and displaying the 16-bit hex value of T on the four 7-segment displays. The instruction SWpush should load the switch values into the lower 8 bits of Treg and push Treg to Nreg. Store a sequence of instructions in the Trom that will multiply the 8-bit hex value on the switches by 25 (decimal). Test the program by setting the switch value to X”35”, step through the instructions, and display the hex answer, X”52D”, on the 7-segment displays.
Demonstrate the operation of your program to a lab instructor. Hand in a listing of your main program and the Trom program. Explain the operation of each instruction in your Trom program.
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