Satyugdarshan Technical Campus,Faridabad

SatyugDarshan Technical Campus,Faridabad

B.Tech(CSE 3rdSem) 1stSessional Examination Sep 2015

Subject: Digital Electronics

Sub Code: EE - 204-F

Time: 1 Hr. 30 MinMM: 30

Note: Question number 1 is compulsory and attempt one question each from section B and Section C. Marks for each question are shown against each.

SECTION ‘A’

Write short note on the following:
Reflected Gray Code

Answer: Gray code is also called as reflected gray code as the (N+1) bit code can be formed by reflecting an N bit code and appending ‘0’ with old code and ‘1’ with newly formed code. The code thus formed differs in one bit value only from one number to next or previous number. An example of forming gray code is shown below:

BCD Addition process, and perform the 68 - 24using 9’s complement.

Answer: For +ve numbers write the 4-bit values for digits

For –ve numbers, take 9’s complement, and write the 4-bit values for digits

Add the numbers

If addition of each nibble > 9 or Carry generated, Add 6 to result

+68 =068

-24= 9’s complement of 024= 999 – 024 = 975

What do you understand by Don’t Care condition, how are they helpful in solving the equation using K-Map

Answer: Don’t care conditions are those terms whose presence or absence does not matter much, however if they are used properly, they may help in simplifying the equation to great extent. They may be taken as ‘1’ for SOP and ‘0’ for POS if they help in forming the octet, quad or pair.

Signed number representation, and write the advantages of 2’s complement representation over 1’s complement system.

Answer:

Signed representation is used to represent both the +ve and the –ve numbers. There are following three type of signed number representation in binary system. These are:

Signed magnitude Number: In this representation one additional bit is needed at MSB position to indicate whether the number is +ve or –ve. Thus if there are N bits then N-1 bits are used for magnitude and Nth bit indicate sign.The range of representable numbers are +/- 0 to +/- 2N – 1.
1st complement representation: In this the magnitude is complemented to get the –ve number. The sign bit is also made equal to ‘1’ to indicate –ve number. For example to represent – 35 using 1’s complement we will do as:

+35 = 0100011

-35 in 1’s complement = 1011100 ; obtained by making ‘0’ as ‘1’ and vice versa

c.2’s Complement representation: The –ve number is representing by 1st taking the 1’s complement of the magnitude and appending 1 at MSB and adding 1 to it. As an example -35 in 2’s complement is written as:

+35 =0100011

-35 in 1’s complement=1011100

Adding ‘1’ +1

We get -35 in 2’s complement= 1011101

Advantage of 2’s complement system:

There is only one zero as against two zero in other representation
Addition and subtraction is performed only by addition process
End around carry is ignored

SECTION ‘B’

(a)Why is it necessary to use Hamming code? A receiver received the following Hamming code 0011100101101 with odd parity. Find the error in the received code and write the correct code that was transmitted by the receiver.

Answer:

13 12 11 10 9 P8 7 6 5 P4 3 P2 P1

00111001011 0 1

We find P1= check ‘1’ leave ‘1’: check 1,3,5,7,9,11,13= Even (Four ‘1’s) Parity

P2= Check 2, leave 2 I.e check 2,3,6,7,10,11= Even (Four ‘1’s) Parity

P4= Check 4, leave 4 I.e check 4,5,6,7,12,13= Even (Two ‘1’s) Even parity

P8= Check 8, leave 8 I.e check 8,9,10,11,12,13= Odd

Parity P8 P4 P2 P1

0 1 1 1= 7; therefore 7th bit is in error

So the correct code transmitted is: 0011101101101

(b) Simplify F(ABCD) = ∑m (0,1,5,9,13,14,15) +d(3,4,7,10,11 using K-Map.

Answer:

1st of all name the boxes as per the minterms. These are shown in bottom right corner of each box.

Enter the ‘1’ against the minterms and ‘X’ against the don’t care terms.

If we consider don’t care terms 3,7,11 as ‘1’s then we can form an octet with terms (1,3,5,7,13,15,9,11)

Similarly, Quad at the top is formed with terms (0,1,4,5) and Quad at bottom (10,11,14,15)

The solution obtained is :

F(ABCD) = A’C’ + AC + D

(a)Explain the Mc-Clusky method of solutions of Boolean equation. Solve the following equation using the Mc-Cluskymethod.F(ABCD) = ∑m (20,28,37,39,48,56)

Answer:

Minterms / m20 / m28 / m37 / m39 / m48 / m56
Binary / 010100 / 011100 / 100101 / 100111 / 110000 / 111000
No. of 1’s / 2 / 3 / 3 / 4 / 2 / 3
Group / Minterms / Binary
ABCDEF / Cheque if used / pair / Minterms
2 / m20 / 010100 / √ / m20-m28 / 01-100 / A’BDE’F’
m48 / 110000 / √ / m48-m56 / 11-000 / ABD’E’F’
3 / m28 / 011100 / √ / m37-m39 / 1001-1 / AB’C’DF
m37 / 100101 / √
m56 / 111000 / √
4 / m39 / 100111 / √

(b)Minimize the following standard POS expression using K-Map and implement the circuit using NOR gates.F = ΠM (0,2,3,5,7)

Answer:

First of all we enter ‘0’ at the given Maxterms.
Now we find that three pair can be formed with ‘0’s

The solution obtained is:

F(ABC)=(A’ + C’) + (A + B’) + (A + C)

SECTION ‘C’

(a) Design a Half Adder.

A half adder is a combinational circuit that adds two bits as shown in the following truth table.

A / B / Sum / Carry
0 / 0 / 0 / 0
0 / 1 / 1 / 0
1 / 0 / 1 / 0
1 / 1 / 0 / 1

Now from the Truth Table we form the following SOP equations for Sum and Carry

Sum =A’B + AB’=A xor B

Carry =AB

(b)Show that a full Adder can be constructed with two half Adders and an OR-gate

Answer

A / B / C / Sum / Carry
0 / 0 / 0 / 0 / 0
0 / 0 / 1 / 1 / 0
0 / 1 / 0 / 1 / 0
0 / 1 / 1 / 0 / 1
1 / 0 / 0 / 1 / 0
1 / 0 / 1 / 0 / 1
1 / 1 / 0 / 0 / 1
1 / 1 / 1 / 1 / 1

The SOP equation from the truth table are written below:

Sum = A’B’C + A’BC’ + AB’C’ + ABC

Carry = A’BC + AB’C + ABC’ + ABC

Simplifying for Sum

The logic circuit diagram using two half adder is shown below

(a) What is a magnitude comparator? Design a 2-bit magnitude comparator

A magnitude comparator is a combinational circuit that compares two numbers and results in equal, less than or greater than depending on the magnitude of the two numbers. This is shown in the truth table below where A and B are two 2-bit numbers.

Functional table for two bit comparison

Input A / Input B / Outputs
A1 / A0 / B1 / B0 / A>B / A<B / A=B
0 / 0 / 0 / 0 / 0 / 0 / 1
0 / 0 / 0 / 1 / 0 / 1 / 0
0 / 0 / 1 / 0 / 0 / 1 / 0
0 / 0 / 1 / 1 / 0 / 1 / 0
0 / 1 / 0 / 0 / 1 / 0 / 0
0 / 1 / 0 / 1 / 0 / 0 / 1
0 / 1 / 1 / 0 / 0 / 1 / 0
0 / 1 / 1 / 1 / 0 / 1 / 0
1 / 0 / 0 / 0 / 1 / 0 / 0
1 / 0 / 0 / 1 / 1 / 0 / 0
1 / 0 / 1 / 0 / 0 / 0 / 1
1 / 0 / 1 / 1 / 0 / 1 / 0
1 / 1 / 0 / 0 / 1 / 0 / 0
1 / 1 / 0 / 1 / 1 / 0 / 0
1 / 1 / 1 / 0 / 1 / 0 / 0
1 / 1 / 1 / 1 / 0 / 0 / 1

A>B = A1'A0B1'B0' + A1A0'B1'B0' + A1A0'B1'B0 + A1A0B1'B0' +A1A0B1'B0 + A1A0B1B0'
A<B = A1'A0'B1'B0 + A1'A0'B1B0' + A1'A0'B1B0 +A1'A0B1B0' + A1'A0B1B0 + A1A0'B1B0
A=B=A1'A0'B1'B0' + A1'A0B1'B0 + A1A0'B1B0' + A1A0B1B0
The Simplifications for the above Boolean equations:

(a). A>B
G=A1B1' + A0B1'B0' + A1A0B0'
(b) A<B
L=A<B = A1'A0'B0 +A1'B1 + A0'B1B0
(c ) A==B
E=A==B = A1'A0'B1'B0' + A1'A0B1'B0 + A1A0'B1B0' + A1A0B1B0
= A’1A’0B’1B’0 + A’1A0B’1B0 + A1A’0B1B’0 + A1A0B1B0
= A'0B'0( A'1B'1 + A1B1) + A0B0( A'1B'1+A1B1)
= ( A'1B'1 + A1B1)( A'0B'0 + A0B0)
= (A1 ⊕ B1)' ( A0 ⊕ B0)'

(b) Write short note on Multiplexer. Amultiplexer(or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. Amultiplexerof 2ninputs has n select lines, which are used to select which input line to send to the output. In general, a MUX (multiplexer) has 2^N inputs, N control lines and a single output. This is shown in the following figure.

B.Tech(CSE, EE,ECE 5thSem) 1stSessional Examination Sep 2015

Subject: Microprocessor and Interfacing

Sub Code: EE - 309-F

Time: 1 Hr. 30 MinMM: 30

Note: Question number 1 is compulsory and attempt one question each from section B and Section C. Marks for each question are shown against each.

SECTION ‘A’

Write short note on the followings
Bus system of 8085 Microprocessor

Answer :8085 is an 8-bit processor which has 16-bit address line, 8-bit data data bus. The data bus is multiplexed with the lower byte of the address bus, and require external hardware to demultiplex the address and data bus for external interface.

Interrupts in 8085 microprocessor

Answer: An interrupt is a request from an external device for attention of the CPU for carrying out some task for the device. Interrupt can be hardware or software interrupts 8086 supports 5 hardware interrupts and 8 software interrupts. These interrupts are further categorized as maskable or non-maskable which means that they may be blocked (maskable) and which cannot be blocked (Non-maskable), another way of classigying these interrupts are vectored or non-vectored interrupts. A vectored interrupt is one whose address of the ISR is known and the call to specific location is made to service the interrupt. Non-vectored interrupt address has to be supplied by the interrupting device.

The interrupts of 8085 system are:

TRAP: Non Maskable

RST 7.5: Vectored but maskable

RST 6.5: Vectored but maskable

RST 5.5: Vectored but maskable

INTR:

Flag register of 8086 Microprocessor

Answer: Flag register indicate the status of the current operation performed by the CPU(to be more specific inside the ALU). 8086 has a 16-bit flag register of which only 9-bits are used as Flag. 5 of the flags are same as in 8085 microprocessor and four new flags are added. The flag register of 8086 microprocessor is shown below:

15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1
- / - / - / OF / DF / IF / TF / S / Z / - / AC / - / P / - / Cy

These flags are control Flags:

DF: data direction flag used to point to the beginning or end of array
IF: Interrupt Flag, by setting or clearing this flag the interrupt can be disabled or enabled.
TF: Trap Flag is used for single step for debugging operations.

Data Flags:

Carry
Parity
Auxiliary Flag
Zero Flag
Sign Flag
Overflow Flag

Calculation of Physical address in 8086 Microprocessor .2

Answer: The physical address in 8086 system is calculated using the following formula

Physical Address = Segment Register Value x 10 + Offset

For example, if Value in Segment register=1234h, offset is 2345h, then :

Segment address x 10= 1234h x 10h = 12340

offset=+ 2345

Physical Address=14385h

This is a 20-bit address.

SECTION ‘B’

(a) Explain the function of ALE and IO/M’ signals of the 8085 microprocessor. Also explain the need to demultiplex the AD7-AD0 lines. 5

Answer : A high ALE signal is generated during the first T state of a machine cycle by the CPU to enable the latch. During this cycle this signal will activate the latch so that the low order address bus can be separated from the data bus.

IO/M’ signal is a control signal which along with S1,S0, RD’ and WR’ is used for selecting memory or I/O device for read write operation.

Need for Multiplexing: The low order address and the data bus are internally multiplexed in 8086 microprocessor. This multiplexing is done to reduce the number of pins on the IC package. However to interface with the external environment, these buses are required to be separated for proper timing synchronization and operation. This separation of the low order address bus and data bus is called de-multiplexing the buses. To de-multiplexing the address and data bus the CPU generates a high ALE signal to enable the latch to latch the address during the first T state of the machine cycle. This de-multiplexing is shown in the following figure.

(b) (c) WAP to add 10 numbers stored in memory, and store the sum at address 2050h and carry if any at address 2051h. 5

Answer: Assuming that the 10 numbers are stored in memory starting at address 2020h. As we add the carry if any will be incremented in register ‘B’ and accumulator will contain the sum of the numbers. Finally the Sum will be stored at 2050h and carries will be stored at 2051h. The following chart shows the logic for the operation.

The complete program is given beside the flowchart.

3. (a) Write an assembly language program to count the number of 1’s and zeros in a given data. 5

(b)What do you understand by the word addressing mode? Explain the different addressing mode of 8085 microprocessor. 5

Answer:

Addressing Modes:

As we are aware that a data item may reside in internal registers, RAM, may come from input device or can be assigned as immediate as part of an instruction. For accessing each type there is a well defined way or method. Therefore, we can define addressing modes as the methods of accessing the data byte(operands). Addressing mode are of the following type in 8085 microprocessor.

Immediate addressing mode

In this addressing mode the data byte is defined as part of the instruction. 8085 microprocessor supports an immediate to register or immediate to memory assignment, and use the instruction MVI for this purpose.

The general Syntax is : MVI Reg/Mem 8-bit Data

Example:

MVI A, 55h ; Transfers an immediate number 55h to Accumulator

MVI B, 55h ; Transfers an immediate number 55h to Register B

MVI M, 55h ; Transfers an immediate number 55h to Memory pointed by HL pair

Implicit addressing mode:

This addressing mode does not specify any additional data, but the data is implied with the instruction, the data is referred by the name of the instruction. As an example CLA stands for clear the accumulator. Here no additional reference is made to locate the data. Instruction of this type are 1-byte instructions.

Examples:

CMA,STC, CLC, RLC, RRC,RAL, RAR

Register addressing mode:

This addressing mode is used t transfer the data item from source register to a destination register. The source register must be loaded with data before using this instruction. This addressing mode uses MOV instruction for transferring data among registers.

Syntax:

MOV Rd, Rs

Here Rs is source register from the general purpose registers and Rd is the destination register from the general purpose registers.

Examples:

MOV A, B ; Transfers 8-bit data from register B to accumulator

MOV D, E ; Transfers 8-bit data from register E to register D

Direct addressing Mode

The direct addressing mode refers to the data from / to the memory for transfer to or from the registers. Use of this addressing mode require setting the memory pointer. 8085 uses MOV instruction for this purpose.

Syntax:

MOV Rd, M; where Rd is the destination register and M is the memory location pointed by HL

MOV M, Rs; where M is the memory location pointed by HL, and Rs is the source register.

Usage example:

LXI H, 2050 ; Set the memory pointer

MOV B, M ;Transers data from memory location 2050h into register B. This instruction also expects the data byte at location 2050.

Indirect memory addressing mode

In this addressing mode the data is accessed indirectly from the memory. The address from where the data is to be fetched is to be found at other place. 8085 uses instructions such as LDAX, STAX, LHLD, SHLD for indirect addressing. These are explained below:

Example

LDAX [Rp] ; Will load accumulator with data from address given in register pair Rp(BC, DE, HL)

STAX [Rp] ; Will store data given in accumulator in memory at address given in register pair Rp.

LHLD [Rp] ; Loads Register L from address given in Rp, then increment Rp and load H from there.

LHLD [Rp] ; Stores Register L from at address given in Rp, then increment Rp and stores H there.

SECTION ‘C’

(a) Explain the internal architecture of 8086 Microprocessor5

Answer:

The system architecture defines how the processor and components relates to each other. The different components of 8086 are grouped and partitioned logically into two processing units. They are the Bus Interface Unit (BIU) and the Execution Unit (EU) as shown in figure below:

Execution Unit (EU):
The EU consists of a set of general purpose registers (AX, BX, CX and DX) the base and index pointers, the ALU, control unit and the flag register. The EU is where actual processing take place. The instructions from the instruction queue and the data that have been fetched by the BIU are accepted by EU and operate on the data as per the instructions. After an operation the processed data (result) can be taken to memory or other peripheral device for later use. As stated above it has 4 components: Control circuitry, ALU, Flag registers and general purpose registers. The basic functions of these different components are: :

Control Circuits:it directs all the internal operations.
ALU:It is where all logic and arithmetic operations are performed.
General purpose registers:They are used to store data during execution.
Flag registers:It has a 16bit flag register containing 9 flags that are set for certain conditions during any operation.

Bus interface unit (BIU):
The basic purpose of this unit is to generate the address of the instructions and the data. It provides a full 16 bit bidirectional data bus and 20 bit address bus (i.e. Address/Data bus is de-multiplexed here). The BIU is responsible for the fetching of the data and instructions from the memory. It contains the following components.

Segment registers:There are four segment register namely code segment register(CS), data segment register, extra segment register, stack segment register.These register contain the 16 bit segment begining address. The full 20 bit address is however obtained by multiplying segment register value by (10)hex and adding the offset/(instruction pointer value)
Multiplier/adder circuit:The BIU contain a multiplier/ adder unit for calculation of the instruction/data address.
Instruction Pointer:The instruction pointer points to the address of the instruction. It is a 16 bit address and thus can point to the 64KB address within a segment.
Queue :8086 has a 6 byte queue, use of the queue allows prefetching of instruction from the memory while the execution of previous instruction is going on in the execution unit.

(b) Explain the Programming Model of 8085 Microprocessor5

The programming model of 8085 consist of an 8-bit accumulator, one flag register, 6 general 8-bit purpose registers, and two 16-bit special purpose registers. These registers are critically required when programming a 8085 processor. The different register in the programming model are explained below:

Accumulator:
Accumulator is an 8-bit register. For processing the numbers, 8085 assumes that one of the numbers is in accumulator. After processing, the result is accumulated in accumulator.

General purpose registers:
8085 has six general purpose registers these are Register B,C,D,E,H,L.All these registers are 8-bits each. These registers can also be used in pair as BC, DE and HL for use as 16-bit data operations.

Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.
The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. The 8085 uses PUSH and POP instructions for stack operations.

Flag Register:
ALU of 8085 contains a special register called a “Flag register” and is an 8-bit register. At the time of design of 8085 only five flags of this register were used and the rest three were reserved. These flags are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit positions in the flag register are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions

5. Explain the flag register of 8086 microprocessor. Register B has 65H and the accumulator has 97H. Subtract the content of register B from the content of the accumulator. Also give the flag statusin 8086 Microprocessor system 10

Answer: