4. Digital Logic

inverter -- NOT gate

NAND gate

logical gates

· NOT

· NAND

· NOR

· AND

· OR

manufacturing technologies

· bipolar

o TTL – transistor-transistor logic

o ECL -- emitter-coupled logic

· MOS – metal oxide semiconductor (PMOS, NMOS, CMOS, etc)

o slower than bipolar

o require less space than bipolar

o require less power than bipolar

o greater packing efficiency over bipolar

A / B / C / M
0 / 0 / 0 / 0
0 / 0 / 1 / 0
0 / 1 / 0 / 0
0 / 1 / 1 / 1
1 / 0 / 0 / 0
1 / 0 / 1 / 1
1 / 1 / 0 / 1
1 / 1 / 1 / 1

boolean function è circuit design

use boolean function to create the truth table
create inverters to generate the complement of each input
create AND gate for each term with 1 in result column
connect AND gates to appropriate inputs
connect output of all AND gates to an OR gate

complete gates

· NAND

· NOR

circuit equivalence -- dual Boolean functions

0 çè 1

AND çè OR

positive logic

· zero volts çè logical zero

· 3.3 volts | 5 volts çè logical one

negative logic

· 3.3 volts | 5 volts çè logical zero

· zero volts çè logical one

Integrated Circuits

Dual Inline Packages – DIP -- chips

· SSI 1 – 10 gates

· MSI 10 – 100 gates

· LSI 100 – 100,000 gates

· VLSI > 100,000 gates

VCC – power

GND – ground

gate delay – propagation time

Combinatorial Circuits

current input values èoutput values (uniquely determined)

control line value set

selects exactly one data input line for output

truth table implementation

result value 1 è input data line VCC

result value 0 è input data line GND

parallel-to-serial converter

n == 3

place byte on the 8 input lines

step control lines sequentially from 000 to 111