Chapter 5:Active components: models & technologies
N-channel MOSFET
Horizontal device
N channel: current transport by electronsEnhancement mode (nonconductive at vGS = 0): no second (opposite) power supply needed for gate bias
Long channel operation: Ohmic region
Long channel operation: Current saturation
Bandwidth limitations
Internal capacitances in combination with series resistance
DELAY: time charge carriers need to travel from source to drain => shorter L
Short channel operation
Very small L, the same VDS => the electrical field rises
Changes ID(VGS) dependency from quadratic to linear
Non-ideal effect 1: substrate currents
In short channel regime
High acceleration => hot electrons = impact ionization of channel atoms creates new electron-hole pairs: add to ID
Non-ideal effect 2: channel length modulation
≈ Early effect
Depletion layer extends further from the drain => shortening the Leff and increase IDS
Increased output conductance, reduces power gain
Non-ideal effect 3: Body-effect (back-gate bias effect)
Channel field changes induced by a varying bulk-to-channel voltage (when bulk-source shorting is not possible)
More negative VB => wider depletion layer => less amount of neg charge => more VGSneeded = VT rises
Non-ideal effect 4: Temperature effects
VT is temperature dependent
Mobility decreases with higher temperature (exp law)
Non-ideal effect 5: Sub threshold condition
Vgs < Vt => Ids > zero
Small currents due to parasitic NPN: n+ source – p bulk – n+ drain
Weak inversion shows low gm, low ft, not interesting for high-speed circuits
Vertical FET
Macroscopically vertical: Drain contact is underneath
Microscopically: channel is still horizontal
Power MOSFETs
On resistance has a positive tempco => no hot spots
a warmer region repels excessive current
Cannot block inverse D-S current: inverse diode present S-D
Linear models of active components
Due to small signal variation around a DC operating point => linearization
Setting the DC operating point
Q-point = quiescent: to be kept stable variable due to: temp, VDD, processor parameters
DC load line = all possible DC combinations
AC load line: dynamic load differs from DC load
One uses sensitivity factors to express IC dependencies
BJT: Hybrid-pi model
Transconductance gM
Base-emitter resistance rpi models SS input resistance
Big BJT have large gM, low small-signal input resistance, large capacitances
Collector-base resistance r0(= BIG) models the early effect
Base series resistance rB models resistance between base contact and eff base region
HF operation is limited: by capacitors: CBE/CB depletion of BE/CB junction
FET
Bulk transconductance gS models body effect
rDS models channel-length modulation
Par. Cap. CGS > CGD
There is also an RG !!
Speed limitations
Transition frequency fT
Defined at weak signals
The frequency at which the magnitude of the common emitter/source short-circuit current gain approximates unity
T is the network (BJT/FET)
Limitations of fT
Ideal current source at the gate
D-S shorted => o info on rG or CGS but has major impact on RF performance
Better definition fMAX
Maximum frequency of oscillation
Frequency at which GMAX (maximum available power) approaches unity
GMAX is reached when input and output ports are simultaneously conjugately matched, but not all devices are stable under such termination conditions => then choose optimum impedance
Assume: CGD can be neglected for input C but nor for ZOUT (determination of the conjugately matched load for maximum power gain)
Half of the power is send trough the Zout
the other half trough the load; PL/PIN must be unity
Transit time effects
Long channel operation: gate admittance has e real part
Negligible below wT/5
Due to distributed nature of t transistor, transit time effects