ECS Interface Library User Guide
1MHz version
Version:Release_v3.1
Last modified: 22.10.2008
Prepared by: Hui Gong, Alex Gong, Hou Lei,Dai Gang and Guido Haefeli
Note that this document is strongly related to the TELL1 firmware version!
Document status sheet
3.1 / 22.10.2008 / Version increased to be compatiable with firmware.3.0 / 03.10.2008 / 1．Added a function to check FE data for all sub-detectors. If no FE data accompanies TTC/ECS trigger, MEP generator will send out empty event. This function is defiantly disabled Add FE_data_check_ctrl_register
2．Added serious error throttle for all sub-detector.
3．Added TTC parity check
4．Added periodic NZS bank scheduler.
5．Insert forced stop cycles for GBE flow control.
6．GBE support auto-negotiation mode
7．Add a tell1_selftest routine for hardware test
8．L0fe_reset with one clock cycle delay!
9．Added new data rate monitor registers for framer allowed data rate
10．Added new parameters into the common part of cfg file.
11．Some logic optimized for better timing
12．byte calculation error fixed in SL_PP_Linker
New parameters added to the tell1 recipe, all default value can be used.
_L0013:___ 0x[ 0]
_L0030:___ 0x[ 0]
_L0031:___ 0x[ 0]
_L0032:___ 0x[ 0]
_L0033:___ 0x[ 0]
_L0041:___ [ 0]
Detector specific part
13．Re-design the hdl and C codes for L0PUS.
14．Added data generation and error check functionality for L0DU.
15．Modified RX readout fsm and the setting of RX event size for L0DU.
16．header correction for ST
17．arx links fdisable or ST.
18．error bank parser Corrected for OT.
19．EHCAL and PSSPD specific HDL codes received from Nicolas on May 26. Fixed the fifo underflow bug for PSSPD by Nicolas on May 31.
20．Added L0MUON specific HDL codes received from Jean-Pierre on May 20
21．VELO Beetle pseudo header polarity correction
22．fix ST/VELO algorithm bugs in both Firmware and Emulator (Pedestal/CMS/Cluster)
23．NZS in case of error for VELO/ST (this cause TELL1 data structure change)
2.7 / 02.07.2008 / Integrate OT specified registers/rams description provided by Mirco.
Add No FE data check parameter register
Correct NZS_BANK_SCHEDULE_CTRL_REG0/1 describrition
Add Pesudo_header_polarity bit for velo in PP_CTRL_REG1
Add nzs_for_error_enable bit for velo/st in PP_CTRL_REG1
Add GBE_force_idle_cycle in SPI3_RX_CTRL_REG for GBE bandwidth restriction.
2.6 / 21.5.2008 / Added header correction value 4 per link including correction for last two header bits for ST.
Added Proc ID register for L0PUS.
Added L0DU specific registers and RAMs
Added PP serious error throttle control bit in PP_CTRL_REG1
Added SL serious error throttle control bit in THRO_CTRL_REG
Added No FE data check functionality, which can be enabled of disabled by setting bit 30 of SL_CTRL_REG0
Added TTC dest IP Parity Check
Added ARX link control register for ST
Added NZS bank schedule register 0 and register 1
Add GBE wait after Pause frame in SL
Add ST select PCN, one per PP FPGA
2.5 / 14.4.2008 / 1． Fix the bug in C code about the generation of ModelSim simulation init file (set_mem.do) for L0MUON.
2． Correct the wrong definition of bit width of SEP data fifo max usage (from 11 to 14) in C code.
Update the ECS document as well: SL_MAX_USE_REG ($0x001054).
3． Fix the bugs that orx link read/write event counts mismatch for L0CAL.
4． Replace two hdl files and fix the bugs that orx link read/write event counts mismatch for MUON.
5． Replace two hdl files for L0Du.
6． Change the scheme that pedestal banks are generated.
ECS document and CFG file generation code are modified as well.
7． Add two menus under C (tell1 control) in console_tell1:
(d) Disable all orx link
(c) Cancel the disable of all orx link
8． Replace detector_specific_vhdl_libraries for EHCAL and PSSPD.
Fixed a bug that ZS Link fifo and ZS data fifo will overflow after a few consecutive triggers.
9． Add a tell1 self test function which is called at the beginning of daq_tell1 and can be called by PVSS.
10． Fix a bug about the definition of ecs_reg_SL_ERROR_MON_REG_N.
ecs_reg_SL_ERROR_MON_REG_N <=
X"00"&
'0' &
pp0_llink_parity_error &
pp0_llink_parity_error &-> pp1_llink_parity_error
pp0_llink_parity_error &-> pp2_llink_parity_error
pp0_llink_parity_error &-> pp3_llink_parity_error
qdr_crc_chk_err &
mep_info_fifo_underflow &
mep_info_fifo_overflow &
"000000" &
ttc_fifo_error;
11． Check MTU size setting in firmware. If ECS setting value is bigger than 8192, MTU size is assigned with 8192, otherwise, MTU size is equal to ECS setting value but 3 LSB are masked as 0. Notice: ECS setting value is equal to cfg file setting value minus 20.
12． Fix a bug that QDR CRC check state machine doesn’t work well when the length of MEP is too big.
13． Fix a bug that EVT_INFO_FIFO, DEST_IP_FIFO, TRIG_TYPE_FIFOand MEP_END_FIFO will overflow in the case that consecutive ECS triggers are sent too frequently.
14. Reduce the usage threshold of SL PP in fifo to make it safer.
15. Velo: The low threshold is not stored in the cluster para reg anymore, it is in the threshold ram, the document 2.4 was still showing it to be in the register
2.4 / 5.3.2008 / Added the low threshold for Velo per strip
Added the FIR coefficients for Velo
Added header correction value per link
Added MCMS enable bit for Velo
ST and VELO header_corr_value link wise, header_corr_threshold per board
ST spill_over_threshold, confirmation_threshold instead of sum_th, there is one value per processor channel (2 per Beetle)
Add parity check error counter for LLink and QDR
Add parity error cnt for Trigger info links
Added pp_error_mon and sl_error_mon registers
2.3 / 11.12.2007 / Add last sent Dest IP sent by ttc register 0x10010AC
Add test reg in PPs and SL 0x4000010, 0x100001C
Add ecs_error_cnt regs again for PP and SL
/ Added the low threshold for Velo per strip
Added the FIR coefficients for Velo
Added header correction value per link
Added MCMS enable bit for Velo
ST and VELO header_corr_value link wise, header_corr_threshold per board
ST spill_over_threshold, confirmation_threshold instead of sum_th, there is one value per processor channel (2 per Beetle)
Add parity check error counter for LLink and QDR
Add parity error cnt for Trigger info links
Added pp_error_mon and sl_error_mon registers
ECS Interface Library User Guide
1MHz version
Version: Release_v2.7
Document status sheet
1.Memory MAP
2. Registers and RAM for “PP”
2.1 Common Registers
PP_RESET_REG ($0x000000)
PP_CTRL_REG0 ($0x000004)
PP_CTRL_REG1 ($0x000008)
ORX_CTRL REG ($0x00000C)
PPTEST_REG ($0x000010)
2.2 Common Monitor registers
CONSTANT_REG ($0x001000)
EVT_ASSEM_CNT_REG ($0x001004)
PP_TRIGGER_CNT_REG ($0x001008)
PP_BANK_CNT_REG0 ($0x00100C)
PP_BANK_CNT_REG1 ($0x001010)
PP_EVENT_CNT_REG ($0x001014)
BER_ERROR_CNT_REG ($0x001018)
BER_RCV_CNT_H_REG ($0x00101C)
BER_ RCV_CNT_L_REG ($0x001020)
INFO_PARITY_ERROR_CNT_REG ($0x001024) reg9
PP_ERROR_MON_REG ($0x001028)
PP_ECS_ERROR_CNT_REG ($0x00102C)
PP_DATE_REG ($0x001034)
PP_TIME_REG ($0x001038)
PP_VERSION_REG ($0x00103C)
ORX_PROBE_REG ($0x001040)
ORX_ SYNC_REG ($0x001044) REALTIME
ORX_ LINK_DISABLE_REG ($0x001048)
FIFO_STATUS_REG ($0x00104C-($0x00104C…0x00104C +11*4)
2.3 User Specific Register VELO (starts from 0x002000)
VELO_ADCCLK_PHY_DLY_REGH ($0x002000)
VELO_ADCCLK_PHY_DLY_REGL ($0x002004)
VELO_ADCCLK_CYC_DLY_REG ($0x002008)
9CLUS_PARA_REG ($0x00200C, $0x002010 …$0x00202C)
ADC_LINK_PROBE_REG ($0x002030)
ADC_LINK_SYNC_REG ($0x002034)
VELO_PHI_REORDER_STRIP_CNT_REG ($0x002038)
VELO_HEADER_CORR_THRESHOLD_REG($0x00203C)
VELO_CLUSTER_NUMBER_MAX_REG($0x002044)
VELO_FIR_COEFFICIENT_REG ($0x002048 …($0x002064 )
8 Registers
VELO_HEADER_CORR_VALUE_REG($0x002068-$0x002084) 8 registers
8 Registers last is register 34
VELO_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.4 User Specific Register ST (starts from 0x003000)
ST_ARX_LINK_CTRL_REG($0x003000)
12CLUS_PARA_REG ($0x003004, $0x003008 …$0x003030)
Removed register for optical links, they are common registers now !
ST_HEADER_CORR_THRESHOLD_REG($0x00303C)
ST_CLUSTER_NUMBER_MAX_REG($0x003044)
ST_HEADER_CORR_VALUE_LINK0_REG($0x003048-$0x003074) 12 registers
ST_HEADER_CORR_VALUE_LINK1_REG($0x003078-$0x0030A4) 12 registers
ST_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.5 User Specific Register OT (starts from 0x004000)
6 OT_OTIS_CTRL_REG($0x004000 ~ $0x004014)
OT_OTIS_STATUS_AB_REG($0x004018)
OT_OTIS_STATUS_CD_REG($0x00401C)
OT_ZS_LINKER_ERROR_V_REG($0x004024)
OT_SYNC_CTRL_REG($0x004028)
OT_OTIS_EVID_MON_REG ($0x00402C)
OT_OTIS_BXID_MON_REG ($0x004030)
OT_OTIS_ID_MON_REG ($0x004034)
OT_OTIS_CNTSTAT_MON_REG($0x004038)
OT_HIST_CTRL_REG($0x00403C)
OT_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.6 User Specific Register MUON (starts from 0x006000)
6 MUON_TU_TYPE_REG ($0x006000 ~ $0x006014)
MUON_HIT_PAD_PROC_CTRL_REG($0x006018)
MUON_ODE_ID_REG1 ($0x00601C)
MUON_ODE_ID_REG2 ($0x006020)
MUON_ODE_ID_REG3 ($0x006024)
MUON_PAD_MAX_NUM_REG ($0x006028)
MUON_HIT_MAX_NUM_REG ($0x00602C)
MUON_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.6’ User Specific Register L0MUON (starts from 0x00C000)
PP_L0MUON_CTRL_REG ($0x00C000)
6 ORX_CONNECTIVITY_TEST_DATA_REG ($0x00C018 ~ $0x00C02C)
2.7 User Specific Register EHCAL (starts from 0x005000)
CAL_CTRL_REG ($0x005000)
EHCAL_FIFO_STATUS_REG (access via common monitor registers) 13 registers
2.7’User Specific Register L0CAL (starts from 0x00A000)
PP_L0CAL_PARA_REG ($0x00A000)
L0CAL_FIFO_STATUS_REG (access via common monitor registers) 12 registers
2.8User Specific Register RICH (starts from 0x009000)
RICH_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.9User Specific Register L0PUS (starts from 0x008000)
L0PUS_FIFO_STATUS_REG(access via common monitor registers) 12 registers
L0PUS_PROC_ID_REG ($0x008000)
2.10User Specific Register BCM (starts from 0x00C000)
BCM_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.11User Specific Register L0DU (starts from 0x007000)
L0DU_DAPIN_SPY_REG ($0x007000)
L0DU_SYNC_EVT_CNT_REG ($0x007004)
L0DU_FIFO_STATUS_REG(access via common monitor registers) 12 registers
2.12 Common RAM blocks
DATA_GEN_RAM SectionA (Address range:0x100000 – 0x1001FF)
DATA_GEN_RAM SectionB (Address range:0x102000 – 0x1021FF)
DATA_GEN_RAM SectionC (Address range:0x104000 – 0x1041FF)
DATA_GEN_RAM SectionD (Address range:0x106000 – 0x1061FF)
DATA_GEN_RAM SectionE (Address range:0x108000 – 0x1081FF)
DATA_GEN_RAM SectionF (Address range:0x10A000 – 0x10A1FF)
TRIGGER_INFO_TEST_RAM (Address range:0x10C000 – 0x10C1FF)
2.13 User Specific RAM blocks VELO (starts from 0x200000)
8 PEDESTAL RAM (Address range: 0x200000 – 0x2000FF, 0x202000-0x2020FF,….,, 0x20E000 - 0x20E0FF)
9 THRESHOLD RAM (Address range: 0x210000–0x2100FF, 0x212000-0x2120FF, … , 0x220000-0x2200FF)
VELO_AVERAGE_HISTOGRAM (Address range: 0x234000–0x237FFF) ram26
VELO_SLOPE_HISTOGRAM (Address range: 0x238000–0x23BFFF) –ram28
8VELO_REORDER_RAM (Address range: 0x23C000–0x23C0FF, … , 0x24A000–0x24A0FF) reserve
2.14 User Specific RAM blocks ST (starts from 0x300000)
12 PEDESTAL RAM (Address range: 0x300000 – 0x3000FF, 0x302000-0x3020FF,….,, 0x316000 - 0x3160FF)
12 HIT_THRESHOLD RAM (Address range: 0x318000 – 0x3180FF, 0x31A000-0x31A0FF,….,, 0x32E000 - 0x32E0FF)
12CMS_THRESHOLD RAM (Address range: 0x330000 – 0x3300FF, 0x332000-0x3320FF,….,, 0x346000 - 0x3460FF)
1 ST_AVERAGE_HISTOGRAM (Address range: 0x348000– 0x349800) –ram36
1ST_SLOPE_HISTOGRAM (Address range: 0x34C000–0x34D800) –ram38
2.15 User Specific RAM blocks OT (starts from 0x400000)
12 OT_HITNUM_HISTOGRAM (Address range: 0x400000–0x4160FC)
OT_DT_HISTOGRAM (Address range: 0x418000–0x4183FC)
2.16 User Specific RAM blocks L0DU (starts from 0x700000)
L0DU_SYNC_SPY_RAM (Address range: 0x700000–0x700400)
3. Registers and RAM for “SyncLink”
3.1 Common control registers
SL_RESET_REG ($0x000000)
SL_CTRL_REG0 ($0x000004)
SL_CTRL_REG1 ($0x000008)
SL_SIMU_CTRL_REG ($0x00000C)
SPI3_TX_CTRL_REG ($0x000010)
SPI3_RX_CTRL_REG ($0x000014)
THRO_CTRL_REG ($0x000018)
SLTEST_REG ($0x00001C)
MEP_PID_REG ($0x000020)
ECS_SIMU_TRIG_NUM_REG ($0x000024)
ECS_SIMU_TRIG_SCHE_REG ($0x000028)
SEP_MSB4_REG ($0x00002C)
PEDESTAL_BANK_SCHEDULE_CTRL_REG ($0x000030)
BANK_HEADER2_REG ($0x000034)
SL_TP_REG ($0x000038)
MTU_SIZE_REG ($0x00003C)
BANK_CLASS_REG ($0x000040)
NZS_BANK_SCHEDULE_CTRL_REG0 ($0x000044)
NZS_BANK_SCHEDULE_CTRL_REG1 ($0x000048)
3.2 Common monitor registers
SL_PP_PROB_REG ($0x001000)
SL_EVT_CNT_REG ($0x001004)
SL_EVT_OUT_CNT_REG ($0x001008)
LLINK_PARITY_ERROR_CNT_REG($0x00100C)
SPI3_TX_MEP_CNT_REG ($0x001010)
SPI3_TX_WORD_CNT_REG ($0x001014)
SPI3_TX_SOP_CNT_REG ($0x001018)
SPI3_TX_EOP_CNT_REG ($0x00101C)
TTC_TRIG_CNT_REG ($0x001020) REALTIME
TTC_TRIG_TYPE_CNT_REG ($0x001024) REALTIME
TTC_DEST_IP_CNT_REG ($0x001028) REALTIME
TTC_RESET_SIG_CNT_REG ($0x00102C) REALTIME
SL_TRIG_CNT_REG ($0x001030) REALTIME
TRIG_INFO_TX_CNT_REG($0x001034) REALTIME
TRIG_INFO_REQ_CNT_REG ($0x001038) REALTIME
TRIG_INFO_FIFO_MON_REG0 ($0x00103C) REALTIME
TRIG_INFO_FIFO_MON_REG1 ($0x001040) REALTIME
MEP_WRITE_CNT_REG ($0x001044)
MEP_READ_CNT_REG ($0x001048)
MEP_MAX_USAGE_REG ($0x00104C)
SL_ERR_LOG_REG ($0x001050)
SL_MAX_USE_REG ($0x001054)
FROZEN_EVID_REG ($0x001058) REALTIME
FROZEN_BCNT_REG ($0x00105C) REALTIME
FRAMER_MAX_USE_REG ($0x001060)
REAL_RATE_REG0 ($0x001064)
REAL_RATE_REG1 ($0x001068)
REAL_RATE_REG2 ($0x00106C)
REAL_RATE_REG3 ($0x001070)
REAL_RATE_REG4 ($0x001074)
SL_FLOWCTRL_MONITOR_REG ($0x001078)
MEP_GT_16K_CNT_REG ($0x00107C)
SL_DATE_REG ($0x001080)
SL_TIME_REG ($0x001084)
SL_VERSION_REG ($0x001088)
SL_TRIGGER_FIFO_USED_REG0 ($0x00108C)
SL_TRIGGER_FIFO_USED_REG1 ($0x001090)
SL_FEM_DV_CNT_REG ($0x001094) REALTIME
SL_DEST_IP_L0_EVID_LSB_ERROR_CNT_REG ($0x001098)
THRO_CNT_REG0 ($0x00109C) –REG39
THRO_CNT_REG1 ($0x0010A0)
THRO_CNT_REG2 ($0x0010A4)
THRO_CNT_REG3 ($0x0010A8)
SL_TTC_LAST_DEST_IP_REG ($0x0010AC)
SL_LBUS_TEST_REG ($0x0010B0-$0x0010CC) 8 x 32-bit
QDR_CRC_ERROR_CNT_REG ($0x0010D0) reg52
SL_ERROR_MON_REG $0x0010D4) reg53
THRO_CNT_REG4 ($0x0010D8) reg 54
TTC_PARITY_ERROR_CNT_REG ($0x0010DC) reg55
3.3 Common RAM blocks
MEP_LOCATION_RAM (Address range: 0x100000 – 0x1001FF)
IPv4_HEADER_RAM (Address range: 0x102000 - 0x1020FF)
INTEL_MAC_LPB_TX_RAM (Address range: 0x104000 - 0x1043FF)
INTEL_MAC_LPB_RX_RAM (Address range: 0x106000 – 0x1063FF)
SEP_GEN_RAM (Address range: 0x200000 – 0x20FFFF)
4. I2C bus address definition
I2C BUS 0 (mixed)
I2C BUS 1 (FPGA bus)
I2C BUS 2 (A-Rx DAC bus)
I2C BUS 3 (GBE Tx card bus)
Appendix: Example codes for C access
1.Memory MAP
Base address:
SyncLink = 0x1000000; PP0 = 0x4000000 ; PP1 = 0x5000000; PP2 = 0x6000000; PP3 = 0x7000000
2. Registers and RAM for “PP”
2.1 Common Registers
The common register region is divided into two parts as control registers part and monitor registers part. The former is used to provide external control/setting signals to the internal TELL1 logic, they are read/write. The latter is used to read out the TELL1 self-generated information like counters, error information, etc. They are read only.
PP_RESET_REG ($0x000000)
Bit / Name / Description / Type / DefaultRegister Description: One cycle@40MHz after written, the register will return to its default value. Used to generate pulses. / 0x00000000
31- 8 / N
7 - 2 / RESERVE0
1 / BER_CNT_RESET / Clear all BER relative counters / W / 0
0 / ADC_CLK_RESET / Re-initial all adc_clk phase / W / 0
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_CTRL_REG0($0x000004)
Bit / Name / Description / Type / DefaultRegister Description: Provide common and basic control signals for PP process. / 0xA0900204
31-24 / PSEUDO_BIT_H_THR / High threshold for generate the pseudo header bits. ADC values higher than this value is treated as logic ‘1’. / R/W / 0xA0
23-16 / PSEUDO_BIT_L_THR / Low threshold for generate the pseudo header bits. ADC values lower than this value is treated as logic ‘0’. / R/W / 0x90
15-12 / READ_LINK_SEL / The monitor registers for each link share the same ECS address, this field is used to select a certain link’s register to read out.( 0-15 for ARX, 0-5 for ORX) / R/W / 0
11 / R_reorder / Choose the R-sensor reordering for VELO / 0
10 / PHI_reorder / Choose the Phi-sensor reordering for VELO / 0
9 / ZS_EN / Enable/disable the zerosuppression suppression / 1
8 / LCMS_EN / Linear CM suppression after re-ordering Enable/disable the common mode suppression / 0
7 / BER_EN / Enable/Disable the Bit Error Rate test function ( For ORX only) / R/W / 0
6 / DATA_GEN_EN / Enable/Disable the internal data generator to replace the actually detector data / R/W / 0
5 / FIR_EN / Enable/disable the FIR ( ARX only) / R/W / 0
4 / REORDER_EN / (VELO only) / R/W / 0
3 / PEDESTAL_UPDATE_EN / Enable/Disable the pedestal auto update feather, with which the pedestal can follow up the base line shift. / R/W / 0
2 / PEDESTAL_EN / Enable/Disable the pedestal subtraction / R/W / 1
1-0 / DATA_SCALE_MODE / After pedestal subtraction, determines how to scale the 11bit down to 8bit
0: saturate to -128 to 127 (VELO only)
1: bit(8..1) (LSB remove)
2: bit(9..2) (2LSB remove)
3: bit(10..3) (3LSB remove) / R/W / 00
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_CTRL_REG1($0x000008)
Bit / Name / Description / Type / DefaultRegister Description: Provide common and basic control signals for PP process. / 0x00000020
31-16 / RESERVE0 / /
17 / NZS_FOR_ERROR_ENABLE / When set this bit to 1, NZS data will be sent if this PP finds error / R/W / 0
16 / Pseudo header polarity / The bit of pseudo value when pseudo_header_value > PESUDO_BIT_H_THR is set by this bit. / R/W / 0
15 / pp_serious_err_throttle_en / 1 = Enable PP serious err throttle. In this case, if a serous error (such as Fifo overflow&underflow errors, hardware errors) is detected on PP FPGA, a throttle will be sent to SL FPGA. SL FPGA will sum up all kinds of throttles to generate a true throttle signal. Since PP serious err throttle is considered as a throttle from PP FPGA, it can be enabled or disabled by configuration of Throttle_PPx_en bit in THRO_CTRL_REG on SL FPGA. / R/W / 0
14 / pp_lbus_test_data_gen / If pp_lbus_test_en is set to ‘1’, a rising edge transition on this bit will cause lbus transmitting part on all PP FPGAs to send 8 lbus test words to SL FPGA at the same time. The lbus test data received by SL FPGA is stored in SL in fifos, from where the test data can be read out by ECS to check lbus. / R/W / 0
13 / pp_lbus_test_en / It this bit is set to ‘1’, PP lbus test is enabled on PP FPGA. The normal data stream will be corrupted.
Otherwise, PP lbus transmitting part (on PP FPGA) works in normal mode. / R/W / 0
12 / MCMS_enable / Mean CM subtraction enable, CM subtraction before re-ordering for the velo / R/W / 0
11 / Histogram_enable / The histogram can only be read if this bit is set to ‘1’, it is not updated during the read operation, set back to ‘0’ to allow the processor to update it / R/W / 0
10 / PP_USED / Bit to indicate that this PP-FPGA is used for DAQ, can be used to disable the chip to sent data to the SyncLink / R/W / 1
9 / force_info_disable / Allows to disable the error bank at PP / R/W / 0
8 / force_info_enable / Allows to force the error bank being created / R/W / 0
7 / header_correction_enable / Enables the header correction for the CMS algorithm for Velo and ST / R/W / 0
6-0 / CLUS_DERAN_USE_THR / Threshold for cluster de-randomizer
(in events. VELO has max 128, OPT max 64) / R/W / 0x20
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
ORX_CTRL REG($0x00000C)
Bit / Name / Description / Type / DefaultRegister Description: O-Rx control bits, bit error rate test mode / 0x3F003F09
31 / RESERVED2 / 00
30 / ENABLE_ALL_ORX / 1=Enable all orx channels
0=Disable all orx channels / R/W / 0
29- 24 / ORX_LCK_REF / Lock to reference output to TLK set 1 for normal operation / R/W / 0x3F
23- 14 / RESERVED1 / 0000000000
13- 8 / ORX_LINK_DISABLE / One hot encoded disable signal for each optical link 1 = disable, 0 = enable
Set 0 for normal operation / R/W / 111111
7-6 / RESERVE0 / 00
5 / ORX_PRBS_EN345 / Pseudo Random Bit Test Enable signal for Optical card channels: 3, 4, 5.
0 = no pseudo random test
1 = enable pseudo random test / R/W / 0
4 / ORX_LOOP_EN345 / Internal loop-back enable signal for Optical card channels: 3, 4, 5.
0 = disable loop-back, means standard operation.
1 = enable Optical card internal loop-back / R/W / 0
3 / ORX_EN345 / Device Enable signal for Optical card channels: 3, 4, 5.
1 = Enable these 3 optical channels
0 = Puts relative circuit of Optical card in power down mode. / R/W / 1
2 / ORX_PRBS_EN012 / Pseudo Random Bit Test Enable signal for Optical card channels: 0, 1, 2.
0 = no pseudo random test
1 = enable pseudo random test / R/W / 0
1 / ORX_LOOP_EN012 / Internal loop-back enable signal for Optical card channels: 0, 1, 2.
0 = disable loop-back, means standard operation.
1 = enable Optical card internal loop-back / R/W / 0
0 / ORX_EN012 / Device Enable signal for Optical card channels: 0, 1, 2.
1 = Enable these 3 optical channels
0 = Puts relative circuit of Optical card in power down mode. / R/W / 1
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PPTEST_REG ($0x000010)
Bit / Name / Description / Type / DefaultRegister Description: To be used for local bus tests / 0x1234ABCD
31..0 / For test use, no functionality / R/W / 1234ABCD
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
2.2 Common Monitor registers
CONSTANT_REG($0x001000)
Bit / Name / Description / Type / DefaultRegister Description: Constant informations / Note
31-24 / Reserved / R / \
7-4 / DETECTOR_ID / used to distinguish different synchronizer designs. Use 0x1 for Velo, 0x2 for ST, 0x3 for OT, 0x4 for Cal, 0x5 for
Muon, 0x6 L0MUON, 0x7 for L0DU, 0x8 L0PUS, 0x9 RICH / R / \
3 / RESERVE0 / \
2-0 / CHIPADDR / Hard-wired chip address. / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
Note: depends on the version settings in common_TELL1_library and user_TELL1_library
EVT_ASSEM_CNT_REG($0x001004)
Bit / Name / Description / Type / DefaultRegister Description: / 0x00000000
31- 16 / Evnt_sync_error_cnt / ORX: Is the number of incomplete received events eg one link enabled missing data no optical data input / R / \
ARX: event in count The number of actual events sent from detector. ( the number of FEM_dv )
15-0 / EVT_OUT_CNT / The number of events assembled in the Rx part. / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_TRIGGER_CNT_REG($0x001008)
Bit / Name / Description / Type / DefaultRegister Description: the number of trigger request and trigger get / 0x00000000
31- 16 / TRIGGER_REQ_CNT / The number of trigger request sent from this PP-FPGA to SL-FPGA / R / \
15-0 / TRIGGER_IN_CNT / The number of trigger information sent from SL-FPGA to this PP-FPGA / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_BANK_CNT_REG0($0x00100C)
Bit / Name / Description / Type / DefaultRegister Description: the number of each bank assembled in this PP-FPGA / 0x00000000
31- 16 / INFO_BANK_CNT / The number of information bank / R / \
15-0 / CLUS_BANK_CNT / The number of cluster bank / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_BANK_CNT_REG1($0x001010)
Bit / Name / Description / Type / DefaultRegister Description: the number of each bank assembled in this PP-FPGA / 0x00000000
31- 16 / ADC_BANK_CNT / The number of adc value bank / R / \
15-8 / PEDE_BANK_CNT / The number of pedestal bank / R / \
7-0 / RAW_BANK_CNT / The number of raw bank / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_EVENT_CNT_REG($0x001014)
Bit / Name / Description / Type / DefaultRegister Description: the number of events assembled in this PP-FPGA / 0x00000000
31- 0 / EVENT_CNT / The number of event sent from PP to SL / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
BER_ERROR_CNT_REG ($0x001018)
Bit / Name / Description / Type / DefaultRegister Description: Bit Error Rate test, the number of error detected.
For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select.
31-24 / BER_WORD_JUMP_CNT / BER errors caused by the counter shift / \
23-0 / BER_BIT_JUMP_CNT / Ber errors caused by the counter mismatch / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
BER_RCV_CNT_H_REG ($0x00101C)
Bit / Name / Description / Type / DefaultRegister Description: Bit Error Rate test, the bit63-32 of the number of received words.
For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select.
31-0 / BER_RCV_CNT_H / ( b63-b32) / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
BER_ RCV_CNT_L_REG ($0x001020)
Bit / Name / Description / Type / DefaultRegister Description: Bit Error Rate test, the bit31-0 of the number of received words.
For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select.
31-0 / BER_RCV_CNT_L / ( b31-b0) / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
INFO_PARITY_ERROR_CNT_REG ($0x001024) reg9
Bit / Name / Description / Type / DefaultRegister Description:Counter for the number of parity errors on the trigger info bus driven by SL and received by pp fpgas
31 / SL_fifo_almost_full / The current value of SL_fifo_almost_full signal on PP FPGA, which is monitored here to check if the hardware connection of this signal on PCB is correct or not, just as a part of lbus test. / R
30..8 / reserved
7..0 / Error cnt / 8-bit parity error cnt / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_ERROR_MON_REG ($0x001028)
Bit / Name / Description / Type / DefaultRegister Description:Counter for the number of parity errors on the trigger info bus driven by SL and received by pp fpgas
31 / Fifo_7 / Overflow info / R
30 / Fifo_7 / Underflow info / R
…. / … / …
17 / Fifo_0 / Overflow info / R
16 / Fifo_0 / Underflow info / R
15..1 / reserved / R
0 / Info_parity_error / Bus data transmission error, used for EvID,BCnt (trig infor) transmission from SL to PPs / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_ECS_ERROR_CNT_REG($0x00102C)
Bit / Name / Description / Type / DefaultRegister Description: the ECS access error count / 0x00000000
31- 8 / RESERVE0 / N
7-0 / ECS_ERROR_CNT / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_DATE_REG ($0x001034)
Bit / Name / Description / Type / DefaultRegister Description: Automatically generated compilation date of the firmware. / \
31-0 / DATE / ddmmyyyy / R / \
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_TIME_REG ($0x001038)