Experiment -9:Binary Synchronous Counter

AIM:Design, and verify the 4-bit synchronous counter.

OBJECTIVE:

i).To understand the design of a sequential circuits.

ii)To implement the theory with a real circuit and verify the working.

THEORY: A synchronous binary counter counts from 0 to 2N-1, where N is the number of bits/flip-flops in the counter. Each flip-flop is used to represent one bit.

OUTPUT / INPUTS
Present State Q3Q2Q1Q0 / Next State Q3Q2Q1Q0 / J3 / K3 / J2 / K2 / J1 / K1 / J0 / K0
0000 / 0001 / 0 / X / 0 / X / 0 / X / 1 / X
0001 / 0010 / 0 / X / 0 / X / 1 / X / X / 1
0010 / 0011 / 0 / X / 0 / X / X / 0 / 1 / X
0011 / 0100 / 0 / X / 1 / X / X / 1 / X / 1
0100 / 0101 / 0 / X / X / 0 / 0 / X / 1 / X
0101 / 0110 / 0 / X / X / 0 / 1 / X / X / 1
0110 / 0111 / 0 / X / X / 0 / X / 0 / 1 / X
0111 / 1000 / 1 / X / X / 1 / X / 1 / X / 1
1000 / 1001 / X / 0 / 0 / X / 0 / X / 1 / X
1001 / 1010 / X / 0 / 0 / X / 1 / X / X / 1
1010 / 1011 / X / 0 / 0 / X / X / 0 / 1 / X
1011 / 1100 / X / 0 / 1 / X / X / 1 / X / 1
1100 / 1101 / X / 0 / X / 0 / 0 / X / 1 / X
1101 / 1110 / X / 0 / X / 0 / 1 / X / X / 1
1110 / 1111 / X / 0 / X / 0 / X / 0 / 1 / X
1111 / 0000 / X / 1 / X / 1 / X / 1 / X / 1

The Logic Circuit

Figure shows one way to build a synchronous counter with positive-edge-triggered flip-flops (we can also use negative-edge-triggered flip-flops). Since all flip-flops are driven by a common clock pulse in parallel, the correct binary word appears at the output after one propagation time.

The four flip-flops used in the counter are connected as per the K-Map solution as follows:

  1. Least significant FF inputs J0 and K0 are tied to high voltage(logic 1).
  2. J1, K1 inputs of 2nd FF are connected to the Q0 output of 1st (least significant) FF.
  3. J2, K2 inputs of the 3rd FF are connected output of AND gate to which the inputs are Q1 and Q0.
  4. J3, K3 input of most significant FF is connected to output of AND gate to which input are Q2Q1Q0.

Operation:

  1. Since J0, K0 are tied to logic 1, the 1st FF toggles on every positive going clock pulse.
  2. 2nd FF toggles on the negative going pulse when Q0 is high (logic 1).
  3. 3rd FF toggles on the negative going pulse when Q1 and Q0 are both high.
  4. 4th FF toggles on the negative going pulse when Q2, Q1 and Q0 are all high.

In other words, a FF toggles on next negative clock edge if all the lower bits are at logic 1s.

Requirement:

IC 747602LED04

IC 740802220 Ohm Resistors04

Power SupplyMultimeter

Precaution:

  • All ICs should be checked before starting the experiment. Keep PIN Diagram of IC with you
  • All the connection should be tight.
  • Always connect ground first and then connect Vcc.
  • Suitable type wire should be used for different types of circuit.
  • Power-off before changing the connections.
  • After completed the experiments switch off the supply of the apparatus

Implementation:

Function table

INPUTS / OUTPUT
PRESET / CLEAR / CLOCK / J / K / Q / Q’
L / H / X / X / X / H / L
H / L / X / X / X / L / H
L / L / X / X / X / ? / ?
H / H / / L / L / Q / Q
H / H / / H / L / H / L
H / H / / L / H / L / H
H / H / / H / H / TOGGLE

Preparation:

Verification:

With the connection as per the K-Map simplified logic equations and the function table, apply clock pulse of about 1 Hz and observe the pattern on the LEDs. We find that the output satisfies the truth table.