WYV57

Optimized Reversible Vedic Multipliers for High Speed Low Power Operations

Parmar, S.

Advance Computing Conference (IACC), 2013IEEE3rdInternational

DOI:10.1109/IAdCC.2013.6514477

Publication Year:2013 Page(s): 1656 – 1663

Project Title: Optimized Reversible Vedic Multipliers for High Speed Low Power Operations

Domain:VLSI

Reference:IEEE

Publish Year:22-23 Feb. 2013 Page(s): 1656 – 1663

D.O.I:10.1109/IAdCC.2013.6514477

Software Tool :XILINX

Language : Verilog HDL

Developed By:Wine Yard Technologies, Hyderabad

Optimized Reversible Vedic Multipliers for High Speed Low Power Operations

Abstract:

Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.

Keywords— Quantum Computing, Reversible Logic Gate, Urdhva Tiryakbhayam, Optimized Design, TRLIC.

Existing method:

Abinary multiplieris anelectronic circuitused indigital electronics, such as acomputer, tomultiplytwobinary numbers. It is built usingbinary adders.A variety ofcomputer arithmetictechniques can be used to implement a digital multiplier. Most techniques involve computing a set ofpartial products, and then summing the partial products together. This process is similar to the method taught to primary schoolchildren for conducting long multiplication on base-10 integers, but has been modified here for application to a base-2 (binary)numeral system.

With the advancement in the VLSI technology, there is an ever increasing quench for portable and embedded Digital Signal Processing (DSP) systems. DSP is omnipresent in almost every engineering discipline. Faster additions and multiplications are the order of the day. Multiplication is the most basic and frequently used operations in a CPU. Multiplication is an operation of scaling one number by another. Multiplication operations also form the basis for other complex operations such as convolution, Discrete Fourier Transform, Fast Fourier Transforms, etc. With ever increasing need for faster clock frequency it becomes imperative to have faster arithmetic unit. Therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them.

Existing multiplier technique:

1.Array based multiplier

2.Radix based multipliers

3.Carry-save array multipliers

4.Wallace tree multiplier…etc.

Proposed method:

Vedic Mathematics is one of the most ancient methodologies used by the Aryans in order to perform mathematical calculations. This consists of algorithms that can boil down large arithmetic operations to simple mind calculations. The above said advantage stems from the fact that Vedic mathematics approach is totally different and considered very close to the way a human mind works. The efforts put by Jagadguru Swami Sri Bharati Krishna Tirtha Maharaja to introduce Vedic Mathematics to the commoners as well as streamline Vedic Algorithms into 16 categories or Sutras needs to be acknowledged and appreciated. The Urdhva Tiryakbhayam is one such multiplication algorithm which is well known for its efficiency in reducing the calculations involved.

The development in the field of nanometer technology leads to minimize the power consumption of logic circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. In the digital design, the multipliers are widely used process. So, the reversible logic gates and reversible circuits for realizing multipliers like 2bit,4bit…etc. reversible multiplier using reversible logic gates is proposed. The proposed design leads to the reduction of power consumption compared with conventional logic multipliers.

Applications:

  1. Digital systems designing
  2. Digital signal processing
  3. Multiplication
  4. Arithmetic and Logic Unit (ALU)
  5. Microprocessors

Advantages:

  1. Area Efficient adders.
  2. Low power adders.
  3. High speed adders.

Conclusion:

The focus of this paper is main speed multiplier which is done using reversible logic gates. The efficiency of characterized in terms of para number of constant inputs, g gates utilized to realize the low value of these parameters more parameter called TRLIC had b as sum of all cost metrics of t cost is a parameter that dire quantum circuit. Also lower T the quantum cost, hence lower Besides imbibing the design generated within the circuit. The further optimization total logical costs is under p work. Number of garbage outputs (from 9 gns 1 and 2) and the gate count the designs). Also there is a of all the ripple carry adders by cation involving replacement of Gate and reduction in garbage e reason. Therefore, even if the slightly, the decrease in the t have totally nullified its effect. n the TRLIC is at 5.86% which e maximum improvement stand o from the table it is clear that minimum gate count as well as compared to all other multipliers constant inputs is better than 10 can say that the design is very o others studied here. only to design a low power high e by constructing the multiplier he procedure is carried out so as n as compared to those in thea reversible logic circuit is parameters such as quantum cost, garbage outputs and number of logic implementation. Lower the e efficient is the design. The proposed which is defined the given design. The quantum effectively reflects the delay of the TRLIC implicitly means lower power is the delay and vice versa. the proposed designs also reduce thefan-out previously proposed design n of the circuit in terms of the progress and is taken as future work.

Circuit Diagram:

Screen shots:

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