Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone:408.943.6900 Fax: 408.943.7943
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Background Statement for SEMI DRAFT Document 4624B (rev. 16)
NEW STANDARD: SPECIFICATION FOR DEVELOPMENTAL 450 mm DIAMETER POLISHED SINGLE CRYSTAL SILICON WAFERS
Note: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this document.
Note: Recipients of this document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.
Attached document specifies 450 mm diameter polished single crystal wafers intended for use in research and development of process and metrology equipment and fabrication processes required to manufacture high-density integrated circuits on 450 mm diameter single crystal silicon wafers. It can also be used to establish the techniques and metrology necessary to support a dimensional specification for 450 mm diameter circuit-quality (prime) wafers.
This document should be superseded by dimensional specification and technology-specific guidelines for circuit-quality wafers.
The detailed specifications for 450 mm wafers are organized in three categories to assist manufacturers in choosing the most cost effective wafers for a given application:
- Particle monitors, intended for use in evaluating the particle contamination added by a process tool.
- Lithography monitors, for development of lithographic and patterning equipment and processes.
- Other monitors, suitable for use in process and inspection equipment development (other than particle counting or lithography development).
The developmental wafers dimensional requirement are identical to the 450 mm mechanical handling wafers, published in SEMI M74, except wafer diameter tolerance, that was tightened to 0.1 mm, to better reflect wafer handling and some process equipment needs.
When specifying the wafer edge profile the customers must select one of two options, a parameter based profile or a template based edge profile.
The previous draft of this document, 4624A, was reviewed at SEMICON® Japan 2009. A number of editorial clarifications were made, which are reflected in the present draft. In addition to these changes, some additional clarifying notes are added to Table 1 and a Related Information section is added to clarify the related equipment requirements for use with the edge profiles specified in this document.
The results of this document will be reviewed at the Int’l 450 mm Wafer TF and will be adjudicated by the NA Silicon Wafer committee during their meetings at NA Spring Meetingsin March 29-30, 2010 in Santa Clara, CA. Please check for the latest meeting schedule.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 1Doc. 4624A SEMI
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone:408.943.6900 Fax: 408.943.7943
hb khghgh1000A4554
SEMI DRAFT Document 4624B
NEW STANDARD: SPECIFICATION FOR DEVELOPMENTAL 450 mm DIAMETER POLISHED SINGLE CRYSTAL SILICON WAFERS
1 Purpose
1.1 The developmental wafers covered by this specification are intended for use in research and development of process and metrology equipment and fabrication processes required for manufacturing high-density integrated circuits on 450 mm diameter single crystal silicon wafers. They can also be used to establish the techniques and metrology necessary to support a dimensional specification for 450 mm diameter circuit-quality (prime) wafers.
2 Scope
2.1 This specification covers dimensional and crystallographic orientation requirements for 450 mm diameter, polished single crystal silicon wafers needed in development. This document should be superseded by dimensional specification and technology-specific guidelines for circuit-quality wafers.
2.2 A complete purchase specification requires that additional physical properties be specified along with test methods for determining their magnitude. If a test instrument is not available, the acceptancecriteria should be agreed upon between supplier and customer.
2.3 This specification also contains guidance to assist equipment manufacturers and others to specify wafers for use in developing selected process equipment and unit processes.
2.4 The specification for 450 mm diameter mechanical handling wafers used in development of 450 mm semiconductor equipment such as 450 mm wafers carriers, load ports, Automated Materials Handling System (AMHS), and robotics has already been published as SEMI M74.
2.5 This specification is not intended to be a product wafer specification.
2.6 For referee purposes, SI (System International, commonly called metric) units shall be used.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the users of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.
3 Referenced Standards and Documents
3.1 SEMI Standards
SEMI E45 — Test Method for the Determination of Inorganic Contamination from Mini Environments Using Vapor Phase Decomposition-Total Reflection X-ray Spectroscopy (VPD/TXRF), VPD-Atomic Absorption Spectroscopy (VPD/AAS), or Inductively Couples Plasma-Mass Spectroscopy (VPD/ICP-MS)
SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers
SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers
SEMI M13 — Specification for Alphanumeric Marking of Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M33 — Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-Ray Fluorescence Spectroscopy (TXRF)
SEMI M43 — Guide for Reporting Wafer Nanotopography.
SEMI M49 — Guide for Specifying Geometry Systems Equipment forSilicon Wafers for the 130 nm to 22 nm Technology Generations.
SEMI M52 — Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm, 90 nm, 65 nm, and 45 nm Technology Generations
SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces
SEMI M58 — Test Method for Evaluating DMA-Based Particle Deposition Systems and Processes
SEMI M59 — Terminology for Silicon Technology.
SEMI M67 — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR, ESFQD and ESBIR Metrics
SEMI M68 — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD
SEMI M70 — Practice for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site Flatness
SEMI M73 — Test method for Extracting Relevant Characteristics from Measured Wafers Edge Profiles
SEMI M74 — Specifications for 450 mm Diameter Mechanical Handling Polished Wafers
SEMI MF26 — Test Methods for Determining the Orientation of a Semiconductive Single Crystal
SEMI MF42 — Test Methods for Conductivity Type of Extrinsic Semiconducting Materials
SEMI MF81 — Test Method for Measuring Radial Resistivity Variation on Silicon Wafers
SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
SEMI MF533 — Test Method for Thickness and Thickness Variation of Silicon Wafers
SEMI MF534 — Test Method for Bow of Silicon Wafers
SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning
SEMI MF673 — Test Methods for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gage
SEMI MF951 — Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers
SEMI MF1049 — Practice for Shallow Pit Detection on Silicon Wafers
SEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers
SEMI MF1188 — Test Method for Interstitial Atomic Oxygen Content of Silicon by Infrared AbsorptionWith Short Baseline.
SEMI MF1366 — Test Method for Measuring Oxygen Concentration in Heavily Doped Silicon Substrates by Secondary Ion Mass Spectrometry
SEMI MF1389 — Test Method for Photoluminescence Analysis of Single Crystal Silicon for III-V Impurities.
SEMI MF1390 — Test Method for Measuring Warp on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Thickness Variation on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1617 — Test Method for Measuring Surface Sodium, Aluminum, and Potassium on Silicon and Epi Substrates by Secondary Ion Mass Spectrometry
SEMI MF1619 — Test Method for Measurement of Interstitial Oxygen Content of Silicon Wafers by Infrared Absorption Spectroscopy with p-Polarized Radiation Incident at the Brewster Angle
SEMI MF1727 — Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
SEMI MF1809 — Guide for Selection and Use for Etching Solutions to Delineate Structural Defects in Silicon
SEMI MF1810 — Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers.
SEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers
SEMI T3 — Specifications for Wafer Box Labels
SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol
3.2 ANSI Standard[1]
ANSI/ASQC Z1.4 — Sampling Procedures and Tables for Inspection by Attributes
3.3 ASTM Standard[2]
ASTM E122 — Standard Practice for Choice of Sample Size to Estimate the Average Quality of a Lot or Process
3.4 ISO Standard[3]
ISO 17331 — Surface Chemical Analysis — Chemical methods for collection of elements from the surface of silicon-wafer working reference materials and their determination by total-reflection X-ray fluorescence (TXRF) spectroscopy
4 Terminology
4.1 Terms and acronyms associated with silicon wafers and silicon technology are listed and defined in SEMIM59.
5 Wafer Ordering Information
5.1 Purchase orders for silicon wafers furnished to this specification shall include the following items. Values for these itemsare given in Tables 1 and 2.
5.1.1 Developmental wafer monitor category
5.1.2 Crystal Growth Method (see ¶ 6.4).
5.1.3 Conductivity Type and Dopant.
5.1.4 Resistivity or ResistivityRange.
5.1.5 Wafer edge profile type requested (see ¶ 6.5.7).
5.1.6 Lot Acceptance Procedures (see § 7).
5.1.7 Test methods for specified attributes (see § 8).
5.1.8 Certification (if required) (see § 9).
5.1.9 Packing and Package Labeling (see § 10).
5.2 Optional Criteria — The following items may also be specified in addition to those listed above if they are considered to be necessary for the application for which the wafers are to be employed (see Table 1).
5.2.1 Wafer identification mark symbol or symbols.
5.2.2 Wafer dimensional characteristics requirements — As specified in Appendix 1 of SEMI M1.
5.2.3 Particulate contamination (localized light scatterer) requirements (see ¶ 6.6.2).
5.2.4 Surface defect requirements, including surface metal contamination (see ¶ 6.6.3).
5.3 Additional Criteria — Any additional criteria considered to be necessary for the application for which the wafers are to be employed may also be specified, as agreed between supplier and customer (see Table 1).
6 Requirements
6.1 Table 1 and Table 2 contain detailed specifications for 450 mm diameter wafers intended for use in development. The requirements are organized by wafer categories and edge profile specification method. Table 1 details wafer required properties by category to assist manufacturers in choosing the most cost effective wafers for a given application. Table 2 details the different methods for specifying the edge profile requirements.
6.2 Wafer Categories
6.2.1 Particle monitors — Wafers intended for use in evaluating the particulate contamination added by a process tool must have controlled front and back surface defect properties. Consequently, specifications are provided for front surface localized light scatterers (LLSs), edge chips, and scratches on both surfaces. If desired, a specification for back surface LLSs can be negotiated between supplier and purchaser.
6.2.2 Lithography monitors — For development of lithographic and patterning equipment and processes, both surface flatness and surface defects must be carefully controlled.
6.2.3 Other monitors — This column repeats the basic requirements for developmental wafers. Wafers in this category are not intended for use in particle counting or litography and patterning. These wafers are suitable for use in process and inspection equipment development. When used for furnace and thermal processes development wafer back side, edge surface finish and oxygen content are critical issues in connection with the introduction of slip during high temperature processing. Bulk iron, oxidation induced stacking faults, and bulk microdefects all can influence wafer performance in thermal processing and should be controlled for critical tests; appropriate specification levels should be negotiated between supplier and purchaser.
Table 1General Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers
Item#1 / Wafer Category / MeasurementMethod
Particle Monitors / Lithography Monitors / Other Monitors
2-1 / General Characteristics
2-1.1 / Growth Method / Cz or MCz
2-1.3 / Crystal Orientation / (100) / MF26 (x-ray)
2-1.4 / Conductivity Type / p / p or n / M1, MF42
2-1.5 / Dopant / B / B or P / M1, MF1389
2-1.6 / FQA radius #2 / 223 mm
2-1.8 / Wafer surface declination in respect to crystal orientation / On-orientation 0.0001.000 / MF26 (x-ray)
2-2 / Electrical Characteristics
2-2.1 / Resistivity #2
p type wafers
n type wafers / 0.005 - 100 Ω·cm / 0.5 - 100 Ω·cm / M1, MF673
Not specified / 1-20 Ω·cm / M1, MF673
2-2.2 / Radial Resistivity Variation (RRG)#4 / <10% / M1, MF81
2-3 / Chemical Characteristics
2-3.1 / Oxygen Concentration / Not specified / Customer Specified / M1, MF1188, MF1366
2-3.2 / Radial Oxygen Variation#5 / Not specified / 10% / MF951
2-4 / Structural Characteristics
2-4.1 / Dislocation Etch Pit Density / 10/cm2 / M1, MF1809
2-4.2 / Slip / None / MF 1809
2-4.4 / Twin Boundary / None / MF1809
24.5 / Swirl / None / MF1809
2-5 / Wafer Preparation Characteristics
2-5.1 / Wafer ID Marking#6 / SEMI T7 / T7
2-5.7 / Edge surface conditions / Polished#7
2-5.8 / Back surface condition / Polished#7
2-6 / Dimensional Characteristics
2-6.1 / Diameter / 450 0.1 mm / M1, MF2074
2-6.2 / Notch dimensions#8
Depth
Angle /
1.00+0.25 -0.00 mm
900+50-10 / MF1152
2-6.3 / Orientation of Notch axis / <110> 10
2-6.6 / Edge profile / Customer Specified#9 / M1, M73
2-6.7 / Thickness #3 / 925 25 μm / MF533
2-6.8 / GBIR, less than / 10 μm / 3 μm / 10 μm / MF1530
2-6.9 / Bow, max / Customer Specified / MF534
2-6.10 / Warp, max / 100 μm / 50 μm / 100 μm / MF1390
2-6.13 / Flatness/SFQR (26x8mm2 site size) / Not specified / 42 nm / Not specified / MF1530
2-6.14 / Nanotopography / Not specified / Customer
specified / Not specified / M43
2-6.15 / Near Edge Geometry / Not specified / Customer
specified / Not specified / M67, M68, M70
2-7 / Front Surface Chemistry
2-7.1 / Surface Metal Contamination
2-7.1.1 / Sodium / 1 1010 per cm2 / MF1617, E45
ISO 17331
2-7.1.2 / Aluminum / 1 1010 per cm2 / MF1617, E45
ISO 17331
2-7.1.3 / Potassium / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-7.1.4 / Chromium / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-7.1.5 / Iron / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-7.1.6 / Nickel / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-7.1.7 / Copper / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-7.1.8 / Zinc / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-7.1.9 / Calcium / 1 1010 per cm2 / M33, MF1617
E45, ISO 17331
2-8 / Front Surface Inspection Characteristics
2-8.1 / Scratches / None / M1, MF523
2-8.3 / Pits (COP) / Customer Specified / Not specified / M1, MF523
2-8.4 / Haze / Customer Specified / Not specified / M1, MF523
2-8.5 / Localized Light Scatterers 0.045 μm / 0.16 per cm2 / 0.32 per cm2 / M1
(SSIS)
250 per wafer / 500 per wafer
2-8.6 / Edge Chips / None / M1, MF523
2-9 / Back Surface Inspection Characteristics#10
2-9.1 / Edge Chips / None / M1, MF523
2-9.9 / Scratches - Macro / None / M1, MF523
2-9.10 / Scratches - Micro / Customer Specified / M1, MF523
2-9.11 / Localized Light Scatterers / Customer Specified / M1, MF523
#1 Numbers in the left hand column are not necessarily continuous because they follow the numbers in the polished wafer specification order form, Table 1 of SEMI M1.
#2 This FQA radius results in a nominal edge exclusion of 2 mm; the radius of the wafer is to be center referenced.
#3 Measured at Center Point.
#4 Measured between Center Point and a point on a radius 219 mm from the Center Point.
#5 Measured between Center Point and a point on a radius 215 mm from the Center Point.
#6 See Related Information 1 for optional alphanumeric marking.
#7 Implies a surface condition and not a particular processing technique.
#8 See Related Information 2 for discussion of inscribed fiducial mark wafer (“notch-free”).
#9 Edge profile target is defined in Table 2, choose specification method A or B(see ¶ 6.4.7).
#10 Back surface inspection characteristics are impacted by the type of wafer handling. So far no decision about back surface or edge handling in the bare wafer manufacturing has been made.
6.3 Material and Manufacture — The material shall consist of wafers cut from ingots grown by either the normal Czochralski or the magnetic Czochralski method, at the supplier’s option.
6.4 Dimensions and Permissible Variations — Wafers shall conform to the dimensions and dimensional tolerances as specified for the attributes listed in Table 1.
6.4.1 Shape — Although the warp value specified in Table 1 is expected to be adequate for many developmental purposes, it is now recognized that warp, even with correction for gravitational sag, is not a suitable metric for specifying wafer shape for all applications. Processing may induce additional warp.
6.4.2 Sori is an attribute that may be specified as agreed between the supplier and the purchaser in lieu of warp. (see SEMI MF1451)
6.4.3 Bow values will be specified by the customer, depending on his application requirements.
6.4.4 Flatness — GBIR and SFQR are specified in Table 1. NT and ERO values shall meet customer requirements as specified in the purchase order.
NOTE 1: This is a wafer specification. Equipment specifications may have tighter requirements.
6.4.5 Fiducial Mark — A notch in conformance with the dimensions and tolerances as described in SEMI M1 ¶ 6.6.1.
NOTE 2: Customer preferring wafers without a notch, will have the option to use a fiducial mark inscribed on the wafer backside as discussed in Related Information 2.
6.4.6 Back Surface Finish — The back surface shall be polished.
6.4.7 Edge Profile —The edge profile shall conform to one of two sets of requirements listed in Table 2 at all points on the wafer periphery except the notch region. Customers may choose one of two methods of wafer edge profile specifications:
6.4.7.1 Method A — the edge profile is specified by the set of target parameters and their tolerances given in Table 2 (see SEMI M73).