Boolean Algebra and Logic Gates 8

DOC/LP/01/28.02.02

/ LESSON PLAN / LP –CS2202
LP Rev. No: 01
Date: 25-06-13
Page 01 of 06
Sub Code & Name:
CS2202Digital Principles And System Design
Unit : I Branch :IT Semester :III

Unit Syllabus:

BOOLEAN ALGEBRA AND LOGIC GATES 8

Review of binary number systems - Binary arithmetic – Binary codes – Boolean algebra and theorems- Boolean functions – Simplifications of Boolean functions using Karnaugh map and tabulation methods – Logic gates

Objective:

To understand different methods used for the simplification of Boolean functions.

Session
No / Topics to be covered / Time / Ref / Teaching Method
1 /

Introduction to Number System

Binary number system, octal number system, hexa decimal number system.Conversion of number system from one radix to another . / 50m / 1(pp1-14)
2(7-12) / BB
2 / Binary Arithmetic
Binary addition, Binary Subtraction, Binary Multiplication, BCD, ASCII, GRAY CODE and Error correcting codes / 50m / 1(15-24)
2(12-22) / BB
3 / Tutorial for number system and binary operations / 50m / BB
4 / Boolean algebra, theorems Boolean Functions
Simplification of Boolean functions using theorems. / 50m / 1(33-59)
2(26-98) / BB
5 /

Simplifications of Boolean functions using Karnaugh map

Introduction to map method, two, three variable k-maps

/ 50m / 1(64-70) / BB
6 /

Four and five variable maps, simplification of Boolean functions using K-map

/ 50m / 1(70-76) / BB
7 / Tutorial for karnaugh map / 50m / BB
8 /

K-map using don’t care conditions

Simplification of Boolean functions using don’t care conditions / 50m / 1(80-82) / BB
9 /

Simplifications of Boolean functions using tabulation methods

/ 50m / 2(149-167) / BB
10 /

Introduction to logic gates ,Implementation of functions using gates

/ 50m / 1(51-59)
2(101-113) / LCD
11 /

Tutorial for Boolean functions

/ 50m / BB
/ LESSON PLAN / LP – CS2202
LP Rev. No: 01
Date: 25-06-13
Page 02 of 06
Sub Code & Name:
CS2202 Digital Principles and System Design
Unit : II Branch :IT Semester :III

Unit Syllabus:

COMBINATIONAL LOGIC9

Combinational circuits – Analysis and design procedures - Circuits for arithmetic operations - Code conversion – Introduction to Hardware Description Language (HDL)

Objective:

This unit provides the overview of combinational logic, by discussing various topics related to combinational circuits and code conversion.

Session No / Topics to be covered / Time / Books
Referred / Teaching Method
12 /

Introduction to Combinational Logic

Analysis and design procedures for combinational circuits. / 50m / 1(111-115) / BB
13 / Design of Combinational circuit for a given Boolean function.
Discussion with various examples / 50m / 1(115-118) / BB
14 / Design of Combinational circuits for arithmetic operations
Half adder, full adder, binary adder / 50m / 1(119-123) / BB
15 / Tutorial for design of combinational circuit / 50m / BB
16 / carry propagation, binary subtractor, overflow / 50m / 1(123-129) / BB
17 / Decimal adder, binary multiplier, magnitude comparator / 50m / 1(129-133) / BB
18 / Code conversion
Definiton, code conversions examples, gray code to binary conversion. / 50m / 1(116-118) / BB
19 / Problems in code conversion / 50m / BB
20 / Tutorial for code conversion / 50m / BB
21 / Introduction to HDL
Module representation, Gate delays / 50m / 1(99-104) / BB
22 / Boolean expressions, User defined primitives / 50m / 1(104-106) / OHP
23 / Tutorial for HDL / 50m / BB
Continuous Assessment Test – I
/ LESSON PLAN / LP – CS2202
LP Rev. No: 01
Date: 25-06-13
Page 03 of 06
Sub Code & Name:
CS2202 Digital Principles And System Design
Unit : III Branch :IT Semester :III

Unit Syllabus:

DESIGN WITH MSI DEVICES8

Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable logic - HDL for combinational circuits.

Objective:

This unit focuses on advanced concepts of system design like decoders, encoders, multiplexers, demultiplexers and programmable logic

Session No / Topics to be covered / Time / Books
Referred / Teaching Method
24 /

Introduction to MSI

Designing of decoders and encoders / 50m / 1(134-139) / BB
25 /

Design of 8x1 decoders and encoders using 4x1 encoders

/ 50m / 1(134-139)
2(227-229) / BB
26 / Tutorial for design of decoder and encoder / 50m / BB
27 / Introduction to multiplexers.
Designing of multiplexers for various Boolean functions / 50m / 1(141-147)
2(223-226) / BB
28 / Introduction to demultiplexers.
Designing of demultiplexers for various Boolean functions / 50m / 1(141-147)
2(223-226) / BB
29 / Design of 8x1multiplexer and demultiplexersusing 4x1 mux / 50m / 1(141-147) / BB
30 / Tutorial for design of multiplexer and demultiplexer / 50m / BB
31 / Memory
RAM, types of memories, memory decoding, Error detection and correction, ROM., Types of ROM. / 50m / 1(255-276) / LCD
32 / Programmable logic
Programmable array logic(PAL), Programmable Logic array(PLA). / 50m / 1(276-283) / BB
33 / HDL for combinational circuits.
Gate level modeling, data flow modeling, behavioral modeling / 50m / 1(147-160) / BB
34 / Tutorial for HDL Programs / 50m / BB
/ LESSON PLAN / LP – CS2202
LP Rev. No: 01
Date: 25-06-13
Page 04 of 06
Sub Code & Name:
CS2202 Digital Principles And System Design
Unit : IV Branch :IT Semester :III

Unit syllabus:

SYNCHRONOUS SEQUENTIAL LOGIC10

Sequential circuits – Flip flops – Analysis and design procedures - State reduction and state assignment - Shift registers – Counters - HDL for sequential logic circuits, Shift registers and counters.

Objective:

To Learn about sequential circuits, counters, shift registers, and state diagrams

Session No / Topics to be covered / Time / Books Referred / Teaching Method
35 /

Sequential circuits

Introduction and definitions, Introduction to flip flops,Working of SR / 50m / 1(167-172)
3(314-317) / BB
36 / Working of D,T, JK flip flops / 50m / 1(167-172)
3(317-328) / OHP
37 / Analysis and design procedures
Analysis and design of clocked sequential circuits, state equation, state table, state diagram, flip flop input equations. / 50m / 1(180-190)
2(323-345) / BB
38 / Tutorial for design of flip flops / 50m
39 / State reduction and state assignment / 50m / 1(198-202) / BB
40 / Design of Shift registers using flip flops
Serial transfer, serial addition. / 50m / Internet / BB
41 / Counters
Design of Ripple counters. / 50m / 1(227-243)
3(337-340) / BB
42 / Tutorial for design of counters / 50m / BB
43 / Design of synchronous counters / 50m / 1(227-243)
3(341-352) / BB
44 / Design of Ring and Johnson counters / 50m / 1(227-243) / BB
45 / Tutorial for shift register design. / 50m / BB
46 / HDL for sequential logic circuits, registers and counters / 50m / 1(190-198)
1(244-248) / LCD
47 / Tutorial for HDL of registers and counters / 50m / BB
Continuous Assessment Test – II
/ LESSON PLAN / LP – CS2202
LP Rev. No: 01
Date: 25-06-13
Page 05 of 06
Sub Code & Name:
CS2202 Digital Principles And System Design
Unit : V Branch :IT Semester :III

Unit Syllabus:

ASYNCHRONOUS SEQUENTIAL LOGIC10

Analysis and design of asynchronous sequential circuits - Reduction of state and flow tables – Race-free state assignment – Hazards-ASM Chart.

Objective:

This unit deals with analysis and design procedures of asynchronous logic circuits and hazards.

Session No / Topics to be covered / Time / Books
Referred / Teaching Method
48 /

Asynchronous Sequential circuits

Introduction and discussion of Sequential circuits / 50m / 1(342-344)
2(590-594) / BB
49 / Analysis procedure of asynchronous sequential circuits-Transition table, Flow table / 50m / 1(344-352) / BB
50 / Design procedure of asynchronous sequential circuits-Primitive flow table, reduction of Primitive flow table / 50m / 1(360-367)
2(608-619) / BB
51 / Tutorial for design of asynchronous sequential circuits / 50m / BB
52 /

Reduction of state and flow tables

Implication table / 50m / 1(367-373) / BB
53 /

Merging of flow table, Compatible pairs.

/ 50m / 1(374-379) / BB
54 / Tutorial for reduction of state and flow table / 50m / BB
55 / Race-free state assignment-Three-row flow-table,four-row flow-table and multiple row method. / 50m / 1(374-379)
3(520) / BB
56 / Hazards-Hazards in combinational logic circuits / 50m / 1(379-384)
2(657-673) / BB
57 /

Sequential circuits, Essential hazards.

/ 50m / 1(379-384) / BB
58 /

Tutorial for race free state assignment

/ 50m / BB
59 /

Design example for asynchronous sequential circuit-ASM Chart

/ 50m / 1(299-309) / BB
60 / Tutorial for ASM chart / 50m / BB
Continuous Assessment Test – III
/ LESSON PLAN / LP – CS2202
LP Rev. No: 01
Date: 25-06-13
Page 06 of 06
Sub Code & Name:
CS2202 Digital Principles And System Design
Branch :IT Semester :III

Course Delivery Plan:

Week / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14 / 15
I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II
Units / 1 / / 2 / / 3 / / 4 / / 5

TEXT BOOKS: CAT-I CAT-II CAT-III

1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2007.

REFERENCES:

2. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico Publishing House, Latest Edition.

3. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2007.

Prepared by / Approved by
Signature
Name / K.Thaiyalnayaki / Dr. D.Balasubramanian
Designation / Associate Professor / HOD/IT
Date / 25/06/2013 / 25/06/13