CONCORDIA UNIVERSITY
Department of Electrical and Computer Engineering
COEN 6501: DIGITAL SYSTEMS AND SYNTHESIS
Date: Monday 1st, May 2006, 7:00-10:00 PM
Examiner: A. J. Al-Khalili
Time: 3hrs
ALL QUESTION ARE OF EQUAL VALUE
Notes: 1. Hand held calculators are permitted.
2. Answer ALL questions
Question 1
Compare Carry Ripple Adder with the Manchester Carry Adder for 4 bits of data, in terms of Area, Delay and Power.
Question 2
Give an optimum architecture (in terms of Speed) to calculate Z= X2 +Y2, where X, Y are 3 bit unsigned numbers.
Question 3
a) For the circuit given below write down the equation that determines the speed, then calculate the frequency of operation.
b) If the CLK has ± 5% jitter, determine the new clock speed.
XOR delay= 0.8ns, Input loading= 1.8UL, K1= 0.07ns/UL.
AND delay= 0.5ns, Input loading= 1.5UL, K1= 0.05ns/UL.
Inverter: delay = 0.3ns; Input loading= 1.0UL, K1= 0.03ns/U.L.
JK-F/F: TCQ =2.0ns, tsu =0.3ns. Input loading= 2.0UL, K1= 0.10ns/U.L.
Question 4
The circuit shown in the figure below has been initialized at t = -¥. The arrival time of inputs A, B, and C is -¥ sec. The first active edge of the clock of R1& R2 register arrive at t = 0 sec. The signal skew (tcs) in the clock path is 2 ns. Each F/F has:
Register switching time, tcq = 6 ns, set up time, tsu = 4 ns, hold time, th = 2 ns.
a) Determine the arrival times, required times and the slack times for all nodes identified in the figure. Assume a clock rate of 50 MHz.
Do you anticipate any timing problem?
b) Determine the maximum speed of operation.
c) What happens if the clock skew tcs = -7 ns.
Signal / Arrival / Required / Violationa
b
c
d
e
f
g
h
Question 5
a) Draw the state diagram of a FSM that has an input D and output Z, such that the output is always equal to the input and delayed by 2 clock cycles.
b) Follow the sequential circuit design procedure using D flip flops design and implement the circuit.
Question 6
a) For the VHDL code below, draw equivalent circuit diagram placing all variables on the circuit.
library ieee;
use ieee.std_logic_1164.all;
entity cgp_cell is
port (
operand1 : in std_logic; -- Operand 1
operand2 : in std_logic; -- Operand 2
operand3 : in std_logic; -- Operand 3
result : out std_logic); -- Carry Propagate
end cgp_cell;
architecture cgp_cell_arch of cgp_cell is
component and2
port (
operand1 : in std_logic; -- Operand 1
operand2 : in std_logic; -- Operand 2
result : out std_logic); -- Result: Operand1 and Operand2
end component;
component or2
port (
operand1 : in std_logic; -- Operand 1
operand2 : in std_logic; -- Operand 2
result : out std_logic); -- Result: Operand1 or Operand2
end component;
signal temp : std_logic; -- Temporary Variable
begin -- cgp_cell_arch
u0 : and2 port map (
operand1 => operand1,
operand2 => operand2,
result => temp);
u1 : or2 port map (
operand1 => operand3,
operand2 => temp,
result => result);
end cgp_cell_arch;
b) Write a VHDL code “Test Bench” to test the above circuit.
SOLUTIONS
Answer to Question 1.
The Carry Ripple Adder can be designed by cascading Full Adders. Consequently, each Full Adder is designed with two Half Adders plus OR as shown below:
The total gate count is:
Area=4(2AND+2XOR+OR) = 4(2AAND+2AXOR+2AOR)
Power – Depends on number of gates and their switching activity.
The Manchester Adder is shown below:
The carry propagate is achieved using the multiplexer as shown.
Area = 4(1AND+2XOR+1INV+2Transistor)
Answer to Question 2.
Square of any matrix A is:
Using the above and adding x2+y2 we get:
Total of 4 full adders, 6 half adders and 6 AND gates. Delay=2FA+3HA+1AND
Answer to Question 3.
a) There are two candidates for a critical path in the circuit:
1) Feedback through XOR – Path 1;
2) Feedback through AND – Path 2.
For both paths the equation for determining the clock period is
Therefore, Path 1 is the critical path.
T1=2.0+1.12+0.3=3.42 ns
(rounding to the lower value)
b) When there is jitter, the clock signal can change by .
Taking the worst condition:
(2 successive cycles)
T=1.11*3.42=3.8 ns
f=1/T=263 MHz
Answer to Question 4.
a) Example of calculation:
Arrival / Required / Violationa / 14 / 10 / -4
b / 6 / 7 / 1
c / 6 / 5 / -1
d / 11 / 10 / -1
e / 22 / 18 / -4
f / 8 / 4 / -4
g / 8 / 4 / -4
h / 14 / 10 / -4
Yes, there are timing problems.
Path 1: R1-AND-INV-XOR-MUX-R3
Path 2: R1-INV-NAND-XOR-MUX-R3
Path 1 is the critical path.
F=1/Tmax=1/24 ns=41 MHz
When Tcs=-7, Path 2 becomes the critical path.
F=1/30 ns=33.3 MHz – the new max operation speed.
Question 5.
/ / x=0 / x=10 / 0 / 0 / 0 / 1 / 0
0 / 1 / 0 / 0 / 1 / 0
1 / 0 / 0 / 1 / 1 / 1
1 / 1 / 0 / 1 / 1 / 1
Answer to Question 6.
a)
b)
library ieee;
use ieee.std_logic_1164.all;
entity stimulator is
port (
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic);
end stimulator;
architecture dataflow of stimulator is
begin
out1<=’0’; out2<=’0’; out3<=’0’; -- initial settings
-- The architecture of the stimulator can vary and may be presented in a variety of
-- forms. An example would be:
data:
prosess
begin
out1<=’0’; out2<=’0’; out3<=’0’;
wait for 20 ns;
out1<=’0’; out2<=’0’; out3<=’1’;
wait for 20 ns;
out1<=’0’; out2<=’1’; out3<=’0’;
wait for 20 ns;
out1<=’0’; out2<=’1’; out3<=’1’;
wait for 20 ns;
out1<=’1’; out2<=’0’; out3<=’0’;
wait for 20 ns;
out1<=’1’; out2<=’0’; out3<=’1’;
wait for 20 ns;
out1<=’1’; out2<=’1’; out3<=’0’;
wait for 20 ns;
out1<=’1’; out2<=’1’; out3<=’1’;
wait for 20 ns;
-- All eight vectors are generated.
end process;
entity test_bench is
end test_bench;
architecture content of test_bench is
component stimulator
port (operand1, operand2, operand3 : out std_logic);
end component;
component cgp_cell
port (operand1, operand2, operand3 : in std_logic;
result : out std_logic);
end component;
for ST: stimulator use entity work stimulator (content);
for GP: cgp_cell use entity work cgp_cell (cgp_cell_arch);
signal operand1, operand2, operand3, result : std_logic;
begin
ST: stimulator port map (operand1, operand2, operand3);
GP: cgp_cell port map (operand1, operand2, operand3, result);
end (content);
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