Course Assessment Report
CDA4150C: Computer Architecture (Spring 2008)
Course Learning Outcomes and Expected Performance Criteria:
- #1 Outcome (CS Outcome 3): The students shall be able to understand register-transfer-level (RTL) design of control and data path, and use software tools such as Xilinx ISE to simulate hardware designs captured using hardware description language Verilog. Performance Criteria: 60% correct score on each of Midterm Exam Questions 13, 14 and 15, and Laboratory Assignments 1, 2 and 3.
- #2 Outcome (CS Outcome 9): The students shall be able to analyze the computer performance such as CPU execution time and average memory access time. Performance Criteria: 60% score on each of Homework 1 Questions 1-3, Homework 2 Questions 1-2, Midterm Exam Questions 3-6, 16, 19, Homework 3 Questions 1-2, Homework 4 Questions 1, 4, and Final Exam Questions 12 and 14.
- #3 Outcome (CS Outcome 4): The students shall understand the fundamental concepts and techniques in computer architecture, including instruction set architecture, pipelining, memory hierarchy and exploitation of instruction-level parallelism. Performance Criteria: 60% score on each of Homework 1 Question 4, Homework 2 Questions 3-4, Midterm Exam Questions 1, 2, 7-12, 17-18, 20, Homework 3 Questions 3-5, Homework 4 Questions 2, 3, and Final Exam Questions 1-11 and 13.
- #4 Outcome (CS Outcome 2): The students shall be able to work in teams to accomplish a project for design and implementation of a RISC pipeline microprocessor and an application system. Performance Criteria: 60% score on Laboratory Assignment 4.
#5 Outcome (CS Outcome 5): The students shall be able to Error! Not a valid link.
Relationship of the course to the Degree Program Outcomes:
•BSCS Degree Program Outcome 2: All graduating CS majors shall demonstrate their knowledge and ability relating to algorithm design and complexity analysis. (addressed by course outcome #4)(addresses CAC(a), (j)).
•BSCS Degree Program Outcome 3: All graduating CS majors shall demonstrate their knowledge of, and ability to apply, programming fundamentals in at least three programming languages. (addressed by course outcome #1)(addresses CAC(a)).
•BSCS Degree Program Outcome 4: All graduating CS majors shall demonstrate their knowledge and understanding of, and their ability to apply, the concepts, design principles and fundamental algorithms relating to data structures and their manipulation, programming languages, computer architecture and organization, computer operating systems, and computer networks. (addressed by course outcome #3)(addresses CAC(b), (c) & (i)).
•BSCS Degree Program Outcome 5: All graduating CS majors shall demonstrate their effectiveness in technical oral and written communication skills, particularly as these skills apply to the dissemination of technical information to a range of audiences on a range of subjects dealing with computing technology and its applications. (addressed by course outcome #5)(addresses CAC(f).
•BSCS Degree Program Outcome 7: All graduating CS majors shall demonstrate an ability to function effectively on teams to accomplish a common goal. (addressed by course outcome #4 & #5)(addresses CAC(d)).
•BSCS Degree Program Outcome 9: All graduating CS majors shall demonstrate an ability to analyze the local and global impact of computing on individuals, organizations and society. (addressed by course outcome #2)(addresses CAC(g)).
CAC Outcomes for Computer Science
The program enables students to achieve, by the time of graduation:
a)An ability to apply knowledge of computing and mathematics appropriate to the discipline;
b)An ability to analyze a problem, and identify and define the computing requirements appropriate to its solution;
c)An ability to design, implement and evaluate a computer-based system, process, component, or program to meet desired needs;
d)An ability to function effectively on teams to accomplish a common goal;
e)An understanding of professional, ethical, legal, security, and social issues and responsibilities;
f)An ability to communicate effectively with a range of audiences;
g)An ability to analyze the local and global impact of computing on individuals, organizations and society;
h)Recognition of the need for, and an ability to engage in, continuing professional development;
i)An ability to use current techniques, skills, and tools necessary for computing practices.
j)An ability to apply mathematical foundations, algorithmic principles, and computer science theory in the modeling and design of computer-based systems in a way that demonstrates comprehension of the tradeoffs involved in design choices;
k)An ability to apply design and development principles in the construction of software systems of varying complexity.
Relationship of the course to CAC Outcomes:
Course Outcomes / CAC Outcomesa / b / c / d / e / f / g / h / i / j / k
1 / x
2 / x
3 / x / x / x
4 / x / x / x
5 / x
Assessment of Course Outcomes (see chart below) compared against Degree Program Outcomes:
Course Outcome to Program Outcome Mapping - Computer ScienceCDA 4150 - Computer Architecture
Course Outcomes / % of Students Meeting Threshold / CS
#1 / CS
#2 / CS
#3 / CS
#4 / CS
#5 / CS
#6 / CS
#7 / CS
#8 / CS
#9 / CS
#10
1 / 92.3% / 92.3%
2 / 73.8% / 73.8%
3 / 80% / 80%
4 / 92.7% / 92.7% / 92.7%
5 / 93.1% / 93.1% / 93.1%
# greater than 50%/# / 1/1 / 1/1 / 1/1 / 1/1 / 2/2 / 1/1
Course Content and Assessment Plan:
Day /Date
/ Lecture Topic Description / AssignmentsDue / Course Outcome#
Covered / CS Program Outcome Covered / CAC Outcome# Covered
T /
Jan 8
/ Introduction & Syllabus / Prerequisite test / 1, 3 / 3, 4 / a, b, c, iTh /
10
/ Introduction to Verilog / 1 / 3, 4 / aT / 15 / Fundamental Design in Computer Architecture / Laboratory assignment 1 / 2, 3 / 4, 9 / b, c, g, i
Th / 17 / Defining Computer Architecture / 2, 3 / 4, 9 / b, c, g, i
T / 22 / Technology and application trends / 2, 3 / 4, 9 / b, c, g, i
Th / 24 / Quantitative principles for performance evaluation / Homework assignment 1 / 2, 3 / 4, 9 / b, c, g, i
T / 29 / Sequential design in Verilog / Laboratory assignment 2 / 1 / 3, 4 / a
Th / 31 / RTL and Design Synthesis / 1 / 3, 4 / a
T / Feb 5 / Overview of Computer Organization / 3 / 4 / b, c, i
Th / 7 / Single Cycle Implementation, Data path and Control Unit / 1, 3 / 3, 4 / a, b, c, i
T / 12 / Motivation of Pipelining and its Data Path / Laboratory assignment 3 / 1, 3 / 3, 4 / a, b, c, i
Th / 14 / Pipelining Control Unit and forwarding datapath / Homework assignment 2 / 2, 3 / 4, 9 / b, c, g, i
T / 19 / Forwarding control and load-use stalls / 2, 3 / 4, 9 / b, c, g, i
Th / 21 / Instruction-level parallelism, Loop Unrolling / 3 / 4 / b, c, i
T / 26 / Large-scale logic circuit design guideline / Laboratory assignment 4 / 1, 4, 5 / 2, 3, 5, 7 / a, f, j
Th / 28 / Hardware-based Dynamic scheduling / Homework assignment 3 / 3 / 4 / b, c, i
T / Mar 4 / Register renaming / 3 / 4 / b, c, i
Th / 6 / Midterm Exam / 1, 2, 3 / 3, 4, 9 / a, b, c, g, i
T / 18 / Overview of Control Hazards / Lab assignment 4
Milestone #1 / 1, 2, 3 / 3, 4, 9 / a, b, c, g, i
Th / 20 / Delayed Branch / 2, 3 / 4, 9 / b, c, g, i
T / 25 / Branch Prediction / 2, 3 / 4, 9 / b, c, g, i
Th / 27 / Branch target buffers, Superscalar machine / 2, 3 / 4, 9 / b, c, g, i
T / Apr 1 / Cache Concepts / Lab assignment 4
Milestone #2 / 2, 3, 5 / 4, 5, 7, 9 / b, c, f, g, i
Th / 3 / Four cache design principals and Write policy / Homework assignment 4 / 1, 3 / 3, 4 / a, b, c, i
T / 8 / Improving cache performance / 2, 3 / 4, 9 / b, c, g, i
Th / 10 / DRAM/SDRAM / 3 / 4 / b, c, i
T / 15 / TLB / Lab4 demo and team presentation in lab sessions / 1, 3, 5 / 3, 4, 5, 7 / a, b, c, f, i
Th / 17 / Virtual memory / 3 / 4 / b, c, i
Th / 24 / Final Exam / 2, 3 / 4, 9 / b, c, g, i
Assessment Result Details:
Measured Performance of Each Studenton Each Course Learning Outcome
(expressed as % of maximum possible,
i.e. score out of 100 possible pts)
Course Learning Outcomes #1 through #5
Student Code # / Student Degree Program / #1 / #2 / #3 / #4 / #5
1 / CS / 100 / 77 / 76 / 84 / 86
2 / CS / 100 / 82 / 86 / 90 / 90
3 / CpE / 75 / 63 / 71 / 100 / 100
4 / CS / 100 / 90 / 83 / 100 / 100
5 / CpE / 98 / 93 / 85 / 100 / 100
6 / CpE / 92 / 85 / 82 / 74 / 76
7 / CS / 92 / 86 / 89 / 90 / 90
8 / CpE / 64 / 58 / 38 / 90 / 90
9 / CpE / 92 / 81 / 68 / 94 / 94
10 / CpE / 100 / 91 / 87 / 74 / 76
11 / CpE / 75 / 66 / 59 / 94 / 96
12 / EE / 100 / 58 / 32 / 100 / 100
13 / CS / 75 / 71 / 67 / 90 / 90
14 / CS / 0 / 7 / 14 / 100 / 100
15 / CS / 83 / 87 / 86 / 74 / 76
16 / CS / 95 / 83 / 81 / 90 / 90
17 / CS / 100 / 91 / 73 / 100 / 100
18 / CS / 92 / 80 / 68 / 84 / 86
19 / CS / 100 / 74 / 59 / 84 / 76
20 / CS / 92 / 57 / 62 / 74 / 86
21 / EE / 94 / 80 / 70 / 84 / 80
22 / CS / 93 / 78 / 69 / 80 / 70
23 / CS / 100 / 77 / 84 / 70 / 86
24 / CpE / 25 / 80 / 74 / 84 / 86
25 / CS / 92 / 76 / 74 / 90 / 90
26 / CpE / 87 / 86 / 83 / 90 / 96
27 / CS / 100 / 77 / 79 / 74 / 76
28 / CS / 84 / 81 / 81 / 70 / 70
29 / CS / 98 / 69 / 61 / 90 / 90
30 / CS / 0 / 7 / 14 / 94 / 64
31 / CS / 100 / 80 / 74 / 74 / 76
32 / CS / 100 / 89 / 82 / 90 / 90
33 / CS / 50 / 70 / 71 / 74 / 76
34 / CS / 90 / 46 / 43 / 90 / 90
35 / CS / 92 / 87 / 87 / 90 / 90
36 / CpE / 89 / 70 / 55 / 90 / 90
37 / CS / 100 / 73 / 59 / 100 / 100
38 / CpE / 100 / 89 / 86 / 74 / 76
39 / CpE / 100 / 77 / 66 / 100 / 100
40 / CS / 67 / 62 / 57 / 80 / 80
41 / CS / 92 / 81 / 86 / 84 / 86
42 / CS / 84 / 62 / 66 / 70 / 70
43 / CS / 92 / 87 / 86 / 94 / 96
44 / CpE / 94 / 83 / 88 / 90 / 90
45 / CS / 100 / 83 / 84 / 90 / 90
46 / CS / 92 / 87 / 86 / 80 / 80
47 / CS / 100 / 77 / 82 / 90 / 90
48 / CpE / 100 / 83 / 86 / 90 / 90
49 / CS / 98 / 85 / 80 / 90 / 90
50 / CpE / 83 / 56 / 55 / 74 / 76
51 / CpE / 100 / 89 / 87 / 94 / 96
52 / CS / 17 / 73 / 67 / 90 / 90
53 / CpE / 94 / 71 / 74 / 70 / 70
54 / EE / 92 / 69 / 65 / 80 / 80
55 / CpE / 100 / 43 / 58 / 94 / 96
56 / CS / 92 / 88 / 84 / 74 / 76
57 / CpE / 100 / 74 / 78 / 90 / 90
58 / CS / 92 / 41 / 46 / 94 / 96
59 / CS / 100 / 79 / 81 / 94 / 96
60 / CpE / 100 / 89 / 89 / 74 / 76
61 / CpE / 100 / 81 / 77 / 90 / 90
62 / CS / 75 / 92 / 70 / 94 / 96
63 / CS / 100 / 80 / 76 / 90 / 90
64 / CpE / 100 / 86 / 78 / 100 / 100
65 / CS / 100 / 77 / 88 / 100 / 100
Course Learning Outcomes #1 through #5
Course Statistics / #1 / #2 / #3 / #4 / #5
Mean / 87.4 / 74.6 / 71.6 / 92.7 / 93.1
High score / 100 / 92.6 / 89.5 / 100 / 100
Low score / 0 / 7 / 13.9 / 70 / 64
Standard Deviation / 22.4 / 16.9 / 16.7 / 20.5 / 20.6
Course Learning Outcomes #1 through #5
Measurements vs. Criteria / #1 / #2 / #3 / #4 / #5
Expected Performance Criteria (expressed as % of maximum score out of 100 possible pts) / 60 / 60 / 60 / 60 / 60
Number of Students Below Criteria / 5 / 9 / 13 / 0 / 0
Percent of Students Below Criteria / 7.7% / 13.8% / 20% / 0% / 0%
Number of Students Meeting or Exceeding Criteria / 60 / 56 / 52 / 65 / 65
Percent of Students Meeting or Exceeding Criteria / 92.3% / 86.2% / 80.0% / 100% / 100%
Assessment Results Summary:
Results Summary of Course Learning Outcome 1: The Expected Performance Criteria was 60% of which 60 out of 65 students met. Most of the students have successfully satisfied the laboratory work requirements. Few students spent more time on digesting sequential logic concept and concurrent programming statements.
Results Summary of Course Learning Outcome 2: The Expected Performance Criteria was 60% of which 56 out of 65 students met. Most of the students have successfully made good use of the quantitative methods to evaluate the computer performance. Few students spent more time on figuring out how to calculate the average memory access time for a multi-level cache hierarchy.
Results Summary of Course Learning Outcome 3: The Expected Performance Criteria was 60% of which 52 out of 65 students met. Most of the students have successfully mastered the fundamental concepts and techniques in computer architecture. Few students spent more time on digesting the forwarding technique, TLB and physically tagged, virtually indexed cache design.
Results Summary of Course Learning Outcome 4: The Expected Performance Criteria was 60% of which 65 out of 65 students met. All the students have successfully developed a RISC pipelining microprocessor and its application system as a team work.
Results Summary of Course Learning Outcome 5: The Expected Performance Criteria was 60% of which 65 out of 65 students met. All the students have successfully written technical reports on the design and implementation of a complete computer system.
Course Recommendations based on Assessment Results:
There were 65 students who enrolled in the course during Spring 2008. The assessment shows students meeting the Expected Performance Criteria, except for 5, 9, and 13 students below threshold on Course Learning Outcomes 1 through 3, respectively. Thus, recommended changes to the course are minor. Results indicate that multi-level cache hierarchy design is an area that can be strengthened. Additional material on this topic can be added to Homework number 4. Also, students needed more experience with requirements specifications before starting their lab 4 so that module of the course might be increased from 2 lecture days to 3 lecture days to further improve skills based on the assessment results.
Prepared by: Jun Wang Date: May 27, 2008