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Columns #1and #2A

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Blogs:

JB’s Circuit

John’s all a Twitter about communicating at DAC,where Birds of a Feather are coming to roost.

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Verification Vertigo

Get back to basics with Brian Bailey’s fundamental discussion of what verification actual is (and isn’t).

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EDA Thoughts

EDA marketing insider Daniel Payne uncovers the best, from merger rumors to free passes for DAC exhibits.

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Domeika’s Dilemma

Max Domeika asks if you’re “Multicore ready” -- or already racking up the advantagesof Multicore design.

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Taken for Granted

So, which came first, the model or the tool? Crack through the shell game with Grant Martin.

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Pallab’s Place

See the future that the broadcasters are seeing in Pallab Chatterjee’sreview of NAB hardware.

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Tuning in to Jim

If it’s green, it’s silicon as Jim Lipman looks at power trends in semiconductor manufacturing and design.

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Rick's Wireless Networking

Rick Denker finds balance in everything from debug tools to the perennial clashes of Marketing and Engineering.

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Fahrvergnügen'

Change lanes with Juergen Jaeger and have fun driving high-performance verification methodology.

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Koby’s Kaos

Editor Jim K notes that Bligh and Christian had very different management styles, but Bligh’s kept on sailing.

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Column 2B

iDesign:

Important technical articles

Industry viewpoint pieces

Analyst abstracts

Product reviews

» Recent thoughts by the authors of iDesign

Max's Chips and Dips: Apache's New Chip-Package Solution

Apache Announces Sentinel-PI, A Global Chip-Package-System Co-Design and Co-Analysis Solution for Power Integrity.

Design Data Management Improves Productivity - Even for Small Design Teams

Even small teams working on small designs can realize significant productivity benefits by using Design Data Management (DDM).

Max's Chips and Dips: Automated, Full-Chip Mixed-Signal Design Solution

Those clever little rascals at Magma never fail to have something interesting up their sleeves.

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(anyplace if room:)

VISIT

TODAY

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Column #3A

e-Newsletters

Track thelatest industry news and views with our e-newsletters.:

Chip Designer

  • Time’s Up for Clock-Based Buses on Multicore Chips
  • Tiny Ultra-Mobile Computer-on-Module

IP Designer & Integrator

  • Configurable Power Management ASICs – Today’s System Glue
  • IP to Help Locate VOIP Users for 911 Dispatch

NEW!

Coming to a Screen near You:

Chip/Package/Board -- an iDesign Newsletter

Edited by Clive (Max) Maxfield

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(3B)

ASIC-ASSP Prototyping Survey Report

Report ID: CS051608

Price: $299

To learn more contact: John Blyler

(503) 614-1082,

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Chip Design Trends (CDT) Biannual Report – 2007

Available Now!

Report ID: TB10235

Price: $1,950 (One Issue); $2,950 (Two Issues)

To learn more contact: Melissa Sterling at 415.970.1910 or