UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering and Computer Sciences

Last modified on February 17, 2006 by Borivoje Nikolic (bora@eecs)

Borivoje Nikolic Lab #4: Circuit Extraction EECS 141

1. Objective

The main objective of this lab is to familiarize you with the procedure to extract a SPICE netlist from Cadence and to prepare and analyze the simulation.

2. Tasks

a.  Open the inverter layout in Cadence and extract the layout by clicking Verify -> Extract… on the menu. The extraction menu should come up and should look like the picture below. Make sure flat is selected from Extract Method. In the CIW there will be many commands, at the bottom there should “Total errors found: 0”. If you look in your Library Manager, there should be an additional view for your cell, extracted.

b.  Examine the extracted inverter view. There will be simple outlines designating different layers in the layout. The blue polygons are the metal 1 wires, green outlines represent active area, red strips are poly, and orange boxes represent contacts. You should also see large red boxes and bold white lines that stand out from the outlines. These are the ports of your devices and the nets that connect them.

c.  To netlist the extracted cell view, you will need to run Affirma Analog Environment by clicking on Tools -> Analog Environment. Analog Environment is a graphical interface for running and analyzing Spectre (a language similar to SPICE) simulations on circuits. You may find this tool useful for running analysis on your project. For now, we will use Analog Environment to generate SPICE netlists. In the Affirma Analog Circuit Design Environment window click Setup -> Environment…. In the window that opens select hspice from the Include/Stimulus File Syntax field and flat in the Netlist Type field, then click OK. Now go to Setup ->Simulator/Directory/Host…and change the Project Directory field to your lab directory then press OK. If you are prompted to save the state, go ahead press OK. Finally, click Simulation -> Netlist -> Create Final in Analog Environment. You will be able to see the netlist commands in the CIW and a “…successful” line then your netlist should open in a separate window.

d.  Now go back to your command line and in your lab directory go to CELLNAME/hspiceS/extracted/netlist where CELLNAME is the name of your cell. In that directory, your extracted netlist will be called hspiceFinal. Examine the netlist and you will see all the MOS transistors. Make sure the NMOS and PMOS have the correct width, length, drain and source area, and perimeters.

e.  We will not be using the NCSU model libraries, so comment out the lines:

.lib "/ncsu/cadence/local/models/hspice/public/publicModel/tsmc25dP" PMOS

.lib "/ncsu/cadence/local/models/hspice/public/publicModel/tsmc25dN" NMOS

if they are present. Copy the EE141 spice model for TSMC 0.25 to the lab directory.

> cp ~ee141/MODELS/g25.mod .

Then add the line to reference the library,

.lib ‘g25.mod’ TT

for EE141 models. Change the NMOS and PMOS models from the “TSMC25DN” “TSMC25DP” to “NMOS” and “PMOS”, respectively. Finally comment out the Analog Artist options:

.OPTION INGOLD=2 ARTIST=2 PSF=2

+ PROBE=0

f.  Simulate the extracted SPICE netlist to obtain the transient response and the DC transfer characteristics. Use Vdd = 2.5V. The netlist you obtain from extraction will only give you the two transistors. You will have to add the rest of the code for a simulation to run.
Using your results, obtain the following: VOH, VOL, VIH, VIL, VM, NMH, NML from the VTC, and tplh and tphl from the transient analysis.
*Turn in: Layout, extracted SPICE deck, edited SPICE deck, VTC and transient plots, and your calculated values.

g.  Add a 50fF load capacitor in your SPICE deck. Now resize your transistors so that the new circuit will have a transient response (tplh and tphl) within 10% of the original. Modify your layout to reflect these changes, re-extract, and re-simulate. The textbook offers methods by which the new dimensions can be determined.
*Turn in: Your new layout, SPICE deck, transient plots, and your calculated tplh and tphl. Please qualitatively explain your reasoning for the transistor sizing, and hand in your hand analysis.

h.  Complete the tutorial on hierarchical schematic entry in Cadence.
*Turn in: All schematics.

3. Report

For your report, please hand in the following:

·  Printouts of your schematics and layouts from Cadence

·  Printouts of your SPICE input decks (extracted and edited)

·  The manual calculations for the parameters determined in Part 2.

·  A comparison between your hand analysis and SPICE, along with an explanation of the differences.

·  Qualitative reasoning and hand calculations used in your decision for the transistor sizing in Part 2.