Small Smart Systems: Physical Attributes, Modeling and Design for VLSI

Small Smart Systems: Physical Attributes, Modeling and Design for VLSI

When developing small smart systems we will need to account for both abstract high level development, as well as physical implementation. In addition, systems require interfacing with the real world, which usually necessitates the use of sensors and analog to digital circuits. This set of tasks describes our unique capabilities for physical mixed signal VLSI design, and how we propose to further develop these capabilities for application to smart systems. We will organize these capabilities into the following areas:

·  Advanced System Geometry: 3-Dimensional (3D) Integration

·  Mixed Signal VLSI Design (CMOS, ADC, Sensors)

·  Advanced Physical Modeling for VLSI (Interconnects, Power and Chip Heating)

1. 3-Dimensional Integration

At the University of Maryland we are developing the unique capability of fabricating 3D integrated circuits. Currently, integrated circuits are fabricated in two dimensions (2D), meaning we use a planar process which contains only one basic silicon layer. As a result of using only 2D processing, the performance of integrated circuits is limited. For example, clock trees tend to be very long physically. Long interconnect lines gives rise to cross talk and impedance related losses. Lack of isolation between different circuit components give rise to limitations of the circuit types which can be integrated on a single 2D chip. For example, radio frequency components are difficult to integrate with digital circuits due to excessive on-chip digital interference. In addition, sensor elements may require processing techniques which are incompatible with standard CMOS, thereby prohibiting their use with 2D CMOS technology.

We are working the Laboratory of Physical Sciences of the National Security Agency to develop the 3D integration process. We expect to be able to leverage the capabilities developed in that 3-D program to realize advanced integrated systems. 3D integration employs special fabrication techniques where circuits are first fabricated into 2D silicon chips. The chips are then thinned from approximately a millimeter to 20 microns in thickness. The chips are then stacked into 3-D structures. Special interconnect structures and layout geometries need to be employed to facilitate actual fabrication of the 3D systems. We have already developed prototype chips using the MOSIS facility for use in 3D integration. The chips have specialized vertical interconnect structures. An example is shown in Fig. 1. We propose to develop design and routing algorithms which are optimized for 3D integration. In our initial designs, we plan to separate layers according to functionality, with sensing systems on the top external layer, with dedicated analog and digital layers below. Separation between different layer will enable isolation, and hence the integration of a wider range of components. Once the basic separation along the analog and digital functions is achieved, further specialization between layers, which minimize interconnect parasitics, will be explored.

2. Sensors and Analog to Digital Conversion

We plan to design and prototype integrated sensors that include acoustic, visual, and thermal detectors. These sensors will operate on several levels: (a) Individual integrated sensor chips will be able to process their own data and make independent decisions. (b) The individual multi-modal sensors ICs will be networked to enable decisions based on information provided by the network as a whole. The individual sensing elements will be based largely in CMOS and MEMS technologies:

·  Optical sensors will consist of CMOS focal plane arrays;

·  Thermal sensors will be constructed from PN junctions

·  Vibration sensor will be constructed of a MEMS-based microphone.

Each sensor will be associated with the necessary electronics to transform the associated output to an electrical signal that can eventually be processed. When appropriate, the sensors, mixed signal electronics, including analog front-end components, and the digital processing, will be contained on a single chip. We have developed a unique analog to digital converters that we plan implement in our integrated systems. The new ADC uses a typical flash topology, however, instead of using a resistor ladder to differentiate analog levels, an active, transistor based ladder will be employed. This will mitigate typical flash ADC limitations due to excessively large resistive components. The new ADC will be fabricated using the MOSIS facility.

3. Advanced CAD Tools for Integrated System Physical Modeling

As mentioned above, advanced integrated systems will suffer performance limitations due to their physical implementation. Advanced processors are generating as much as 100W, which gives rise to very high operating temperatures. Projections indicate that if the current trend continues, chip temperatures could reach several thousand degrees C. In addition, the loading due to interconnect and I/O pad capacitance/inductance is rivaling the transistor itself as the fundamental physical factor in limiting system speed, thereby adding complexity to Moore’s law. We are developing modeling techniques to address these issues, and propose to build upon them to help achieve robust 2D and 3D integrated systems.

3.1 Develop Software for 2D & 3D System Temperature Profile, Heat Dissipation and Design Chip Cooling Systems

Software Developed: We have developed a new technique for modeling and predicting the temperature inside 2D and 3D IC’s. We developed a mixed-mode simulation technique which predicts temperatures over the entire chip. The model self-consistently calculates the basic transistor characteristics along with chip temperature as a function of position on the chip and operation time. We also developed a methodology which shows where to place micron-sized thermal contacts that facilitate the extraction of heat from the chip. Fig. 2 illustrates the concept of heat generation within the transistors; Fig. 3 shows the thermal network; Fig. 4 is a contour plot of the temperature distribution of a 0.5cm x 0.5cm one million transistor chip; Fig. 5 shows how the maximum chip temperature may be reduced by careful placement of thermal contacts.

Proposed Work:

Software: Having already developed the basic algorithms, we revise our basic model to account for the specific topologies which we will employ in our integrated systems. For example, we will determine the specific thermal networks for different processor structural blocks, as well as analog topologies. We will then use this information as input to our thermal simulator to predict heating of the overall system. We will also use the software to decide exactly where to place the micron scale thermal contacts to maximize the heat transfer out of the circuit. We will simulate the use of different high thermal conductivity contact materials, as well as packaging. We plan to apply our new CAD tools to both 2D and 3D systems to minimize reliability problems induced by excessive circuit heating.

Experimental: We will develop 2D and 3D test structures to measure the temperature inside the circuit. At different locations within the 2D or 3D system, we will design and place diode arrays. By measuring the DC current variation of the individual diodes of the array, we will obtain the temperature distribution inside the IC. This experimental data will be compared with our simulations for CAD calibration. Like most of our initial prototyping, our diode temperature sensor grid will be designed with the help of Cadence tools, and fabricated through MOSIS and LPS.

3.2 Improve IC Interconnect Electromagnetic (EM) CAD Tools for Integrated System Design

To help analyze on-chip interconnect losses we have developed a unique Finite Difference Time Domain-Altenating Direction Implicit (FDTD-ADI) simulator. This new tool solves Maxwell’s equations in the time domain. The unique aspect of this new solver is that it overcomes the Courant limit, which constrains the maximum discrete step when numerically solving partial differential equations. Overcoming the Courant limit facilitates numerical analysis of using both fine and course discrete meshes simultaneously. This capability motivates the use of the simulator for EM effects on chips, which have critical dimensions ranging from nanometers to centimeters. The new simulator shows large interconnect losses due to return currents in the resistive silicon substrate, and dispersion in 2D IC’s (see Fig. 6).

Proposed Work:

Software and Experimental: We will continue our modeling of 2D and 3D interconnect structures to predict the delay, losses, reflections, parasitic coupling and interference of metal-semiconductor transmission lines and vias. We will use Fourier transform and impulse response techniques to develop a methodology to transform our results from time domain simulations to also be applicable to the frequency domain. We will uniquely enhance our simulation tools to self consistently account for EM interconnect phenomena with semiconductor device physics. We will use this new novel software to design 2D and 3D interconnect structures with minimum parasitics. Interconnect test structures will be constructed using the combined technologies of MOSIS and in-house LPS capabilities. Microwave measurements will be taken to calibrate the simulators with the circuit structures. Active logic circuits that are connected by 2D transmission lines will be fabricated and compared with the performance of analogous 3D structures. We will develop IC test structures, separating the digital and analog components on different layers to show reduced noise coupling. Fabrication will be achieved through combined use of the MOSIS and LPS labs.