CSE 670 Design of Embedded Systems Using FPGAsProf. Hanna

Summer 2007

Lab 7 – Combinational and Sequential Multiplication

Many circuits, such as a circuit that performs binary multiplication can be designed as a combinational circuit that requires a single clock cycle or a sequential circuit requiring several clock cycles. In this lab, we will implement both a combinational multiplier and a sequential multiplier. In both cases, we will use a state machine to obtain input from the 8 switches and display the correct output.

  1. Write a VHDL program called Lab7c.vhd that implements the combinational multiplier using the ‘*’ operator from the unsigned library and state machine for collecting input and displaying output shown in Slides6.1:13 and 6.1:14. Be sure to download the slides from the class website. The VHDL code for this multiplier can be found in 6.1:16-26 if you would like to review it. Use the VHDL filesposted on the class website. Add these files to a new Active-HDL project and compile the files with file reorder.
  1. Simulate the combinational multiplier. Use a 25 MHz clock to stimulatethe clk signal. We will bypass the debounce and clock divider. Expand the BTN signal on the waveform using the + sign. Set the stimulator for BTN(3) as a hotkey. When you select hotkey from the list, set the number ‘3’ as the hotkey as shown below, then click ‘Apply’. Now, find the BTN0 signal on your waveform, not BTN(0), but the signal that comes out of the debounce, BTN0. We will set this signal directly since we are not using the debounce circuit in our simulation. Set the stiumlator for BTN0 using the number ‘0’ as the the hotkey. Set the switches to be 16#0A at 0 ns and then 16#1B later in the simulation (such as 1000 ns).

This will allow you to toggle the value of the BTN(3) and BTN(0) signals as you simulate the design. In this example, at 1000 ns the input on the switches will change to 0x1B, the second value. Finally, set the simulation run time to 200 ns and use the ‘Run For’ button to start the simulation. After running for the first 200 ns, press the ‘3’ key to toggle BTN3 (connected to clr) to clear the circuit. Press the ‘Run For’ button again to run the simulation for another 200 ns. Now, press the ‘3’ key again to toggle BTN3 back to 0 and press the ‘0’ key to toggle BTN0 to high. Press the ‘Run For’ button again to run the simulation for another 200 ns. Using this approach, toggle BTN0 back and forth so that the 0x0A and 0x1B are loaded and the multiplication is performed displaying the result on the seven segment displays. Finally, the product should appear at the pout signal.

Hand in a printout of a waveform multiplying 0A times 1B.

  1. Synthesize and Implement the multipler and determine:
  1. the number of slices required by the circuit: ______slices ( _____ % of the chip)
  1. the maximum delay time in the circuit: ______ns
  1. the maximum frequency at which this design could operate: ______MHz
  1. the totalnumber of clock cycles that it will take to perform a multiplication including clock cycles for loading and displaying data:

______cc

  1. the maximum number of multiplications per second (operating at maximum freq):

______mult / sec

  1. Write a VHDL program called Lab7s.vhd based on part 1 that implements an 8- by 8-bit sequential multiplier using the multiplication algorithm shown in 6.1:29. You will need to replace the multiplication symbol ‘*’ with a component that executes the sequential multiplication algorithm. You will also need to adjust the top-level controller, mult_control.vhd, to wait for the multiplication component to finish since it will require multiple clock cycles.
  1. Simulate the sequential multipler. Hand in a printout of a waveform multiplying 0A times 1B.
  1. Synthesize and Implement the multipler and determine:
  1. the number of slices required by the circuit: ______slices ( _____ % of the chip)
  1. the maximum delay time in the circuit: ______ns
  1. the maximum frequency at which this design could operate: ______MHz
  1. the total number of clock cycles that it will take to perform a multiplication including clock cycles for loading and displaying data:

______cc

  1. the maximum number of multiplications per second (operating at maximum freq):

______mult / sec

  1. Turn in a signed copy of Lab7s.vhdindicating that you have successfully tested your design on the protoboard.
  1. Briefly discuss, in one paragraph, the implications that the combinational and sequential versions have on the total design space and execution speed.
  1. Hand in a listing of Lab7s.vhd as well as files that define your datapath and control unit for the sequential multiplier, the waveforms from parts 2 and 5, and this lab handout with the answers to the questions in parts 3, 6, and discussion from 8.

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