Implementation of FSK Modulation and Demodulation Using CD54/74HC/HCT4046A

Texas InstrumentsApplication Report

Sept 2013

Implementation of FSK modulation and demodulation using CD54/74HC/HCT4046A

Mahendra Patel Standard Linear & Logic

ABSTRACT

Intelecommunicationsandsignal processing,frequency modulation(FM) is encoding of informationon a carrier waveby varying theinstantaneous frequencyof the wave.Digital datacan be encoded and transmitted via carrier wave by shifting the carrier's frequency among a predefined set of frequencies—a technique known asfrequency-shift keying(FSK). FSK is widely used inmodems, Radio-teletypeandfax modems, and can also be used to sendMorse code.

Frequency-shift keying(FSK) is afrequency modulationscheme in which digital information is transmitted through discrete frequency changes of acarrier wave. This application report will discuss logic level implementation of BFSK modulator and demodulator using a PLL device HC/HCT4046A. BFSK is the simplest FSK, which uses a pair of discrete frequencies to transmit binary information.

Contents

1.  Introduction

2.  Implementation of Modulator

3.  Implementation of Demodulator

4.  Test circuit waveforms

5.  Schemes to realize modulator-demodulator pair

6.  Conclusion

List of Figures

1.  Block diagram of an HC/HCT4046A in a Typical PLL circuit

2.  Basic block diagram of a PLL as a modulator

3.  Frequency characteristics of VCO operating without offset

4.  Typical modulator schematic

5.  Basic block diagram of a PLL as a demodulator

6.  Typical demodulator schematic

7.  Scheme 1

8.  Scheme 2

9.  Level shifter circuit using LP211

List of Tables

1.  Modulator test circuit results

2.  Demodulator test circuit results

3.  Variation in VCOOUT frequency, p-p voltage and DEMOUT

4.  VCOIN (modulating), VCOOUT (modulated) and DEMOUT (demodulated)

1.  Introduction

Many measurement applications (for example, electric and gas meters) require a way to communicate electronically with a central office so that measured data can be reported back to the central office and new tariffs can be set in the remote site(1). Telephony provides a convenient means of data communication.

This application report will discuss logic level implementation of FSK modulator and demodulator using a PLL device HC/HCT4046A. The HC/HCT4046A, PLL with VCO is a high-speed CMOS IC designed for use in general-purpose PLL applications, including frequency modulation, demodulation, discrimination, synthesis and multiplication.

Figure 1 illustrates functional block diagram of a PLL IC,

1.  The voltage controlled oscillator (VCO) generates a centre frequency locally.

2.  This is compared with the incoming signal frequency using a phase comparator (PC)

3.  PC generates an error voltage Vd, which is fed into VCO after an LPF to shift the frequency of VCO to lock with incoming signal.

Figure 1. Block diagram of an HC/HCT4046A in a Typical PLL circuit

(1)  Schematics in this report are only for reference. Precise implementation can vary from country to country and based on the application, transmission media, etc.

2.  Implementation of Modulator:

Function of modulator uses only VCO as shown in the block diagram below. Values of R1 and C1 determine the frequency range of the VCO. And centre frequency of operation depends upon VCO input, which is digital input signal level for a modulator. Hence high (bit1) and low (bit 0) voltage level of digital input determines actual output frequencies and separation between them.

Figure 2. Basic block diagram of a PLL as a modulator

To design a modulator with maximum and minimum frequency of fMAX and fMIN respectively, following steps are required:

1.  Given fMAX and fMIN, centre frequency fo can be estimated as (fMAX - fMIN)/2.

Figure 3. Frequency characteristics of VCO operating without offset:

2fL=frequency lock range, fo=Centre frequency

2.  Determine the values of R1 and C1 using figure 11-15 given in the device datasheet.

Note that values of these components must satisfy following conditions,

(i)  3kΩ < R1 < 300kΩ,

(ii)  C1 > 40pF and

(iii)  (R1||R2) > 2.7K

Use of R2 to set the offset frequency is optional and can be left open, if not needed.

3.  Figure 16-21 of the device datasheet gives estimate of separation between frequencies for given VCOIN voltage.

1.0V < VCOIN < 0.9VCC is recommended to generate proper oscillation from VCO.

4.  A LPF (R3-C2) is included to minimize the noise at VCOIN pin, which is optional. 3dB Cut off frequency of this filter should be 10 times or higher than the maximum bit rate of modulating signal.

Figure 4. Typical modulator schematic

Example:

A test circuit (VCC = 5V) was implemented to modulate a digital signal with following component values:

R1 = 3kΩ, C1 = 47pF, R2 = open,

R3 = 0Ω, C2 = open

Table 1. Modulator test circuit results

VCOIN (V) / Frequency of VCOOUT (Hz) / VCOOUT peak to peak (V)
1. / 1.0 / 8.22M / 4.6
2. / 2.5 / 17.24M / 3.1
3. / 4.5 / 27.93M / 2.2

Hence by choosing logic 0 as 1V and logic 1 as 4.5V, a frequency separation of 19.7MHz can be obtained.

In practical circuit, frequency separation depends upon the bandwidth availability of the transmission media. Hence by choosing appropriate offset frequency and voltage level of VCOIN signal, expected modulation can be achieved.

With increase in VCOIN (CH1) voltage, frequency of oscillation increases and VCOOUT peak to peak voltage (CH2) decreases as shown in the figure given below.

Waveform 1. VCOIN (CH1) voltage and VCOOUT peak to peak (CH2) variation

3.  Implementation of Demodulator:

Demodulator operates in closed loop mode with PC and an external LPF as shown below,

Figure 5. Basic block diagram of a PLL as a demodulator

To design a demodulator with maximum and minimum frequency of fMAX and fMIN respectively (which is same as that of modulator), following steps are required:

1.  Use same value of R1 and C1 as that of modulator.

2.  While using PC1, the capture range depends on the LPF (R3-C2) characteristics and can be made as large as the lock range. For PC2, capture range is equal to lock range and is independent of the LPF.

3.  Since leakage current can affect the VDEMOUT, a load resistor (R5) from this pin to GND in the range of 50k to 300k is recommended.

Figure 6. Typical demodulator schematic

Example:

A test circuit (VCC = 5V) was implemented to demodulate a signal using PC2 with following component values:

R1 = 3kΩ, C1 = 47pF, R2 = open,

R3 = 36kΩ, C2 = 120pF

Table 2. Demodulator test circuit results

VCOIN(V)
at modulator / Frequency of SIGIN (Hz)
At demodulator / SIGIN peak to peak (V)
At demodulator / DEMOUT (V)
At modulator
1. / 1.0 / 8.22M / 4.6 / 1.28
2. / 2.5 / 17.24M / 3.1 / 2.5
3. / 4.5 / 27.93M / 2.2 / 3.76

Hence by choosing 3.5Vp-p VCOIN and frequency separation of 19.7MHz at modulator, DEMOUT of 3.76 – 1.28 = 2.48Vp-p can be obtained.

4.  Test Circuit Waveforms:

Waveforms below show variation in following with change in VCOIN voltage,

(i)  VCOOUT frequency,

(ii)  VCOOUT of modulator or SIGIN of demodulator peak to peak voltage and

(iii)  Corresponding DEMOUT voltage.

Table 3. Variation in VCOOUT frequency, p-p voltage and DEMOUT

Condition at Modulator / Demodulator Waveforms:
CH1: SIGIN and CH2: DEMOUT
1. / VCOIN = 1V /
Waveform 2. For VCOIN = 1V
2. / VCOIN = 2.5V /
Waveform 3. For VCOIN = 2.5V
3. / VCOIN = 4.5V /
Waveform 4. For VCOIN = 4.5V

Following waveforms show VCOIN (level shifted digital modulating signal), VCOOUT (modulated signal) and corresponding DEMOUT (demodulated signal) at different frequencies of digital signal.

Table 4. VCOIN (modulating), VCOOUT (modulated) and DEMOUT (demodulated)

VCOIN / DEMOUT / Waveforms:
CH1: VCOIN, CH2: VCOOUT, CH3: DEMOUT
1. / pk-pk (V)=3.44V
Frequency=1kHz / pk-pk (V)=3.12V
Mean (V)=2.74V /
Waveform 5. For VCOIN frequency = 1kHz
2. / pk-pk (V)=3.52V
Frequency=5kHz / pk-pk (V)=3.20V
Mean (V)=2.62V /
Waveform 6. For VCOIN frequency = 5kHz
3. / pk-pk (V)=3.60V
Frequency=10kHz / pk-pk (V)=3.28V
Mean (V)=2.64V /
Waveform 7. For VCOIN frequency = 10kHz
4. / pk-pk (V)=3.60V
Frequency=20kHz / pk-pk (V)=3.12V
Mean (V)=2.69V /
Waveform 8. For VCOIN frequency = 20kHz
5. / pk-pk (V)=3.52V
Frequency=30kHz / pk-pk (V)=3.04V
Mean (V)=2.72V /
Waveform 9. For VCOIN frequency = 30kHz
6. / pk-pk (V)=3.52V
Frequency=40kHz / pk-pk (V)=2.88V
Mean (V)=2.71V /
Waveform 10. For VCOIN frequency = 40kHz

It can be concluded from the above waveforms that, it is difficult to use the DEMOUT signal as it is, at higher frequency of modulating signal. Hence, a Schmitt trigger can be used with appropriate threshold and hysteresis to get a clean demodulated signal with sharp rising and falling edges.

5.  Schemes to realize modulator – demodulator pair

This section describes various FSK modulation-demodulation schemes briefly. It is important to consider the limitations of each technique before using it for a specific application. In each case, frequency used to represent digital data after FSK modulation should be hundred folds or higher that of digital data rate to ensure correct bit duration for each bit after demodulation.

5.1  Scheme 1:

In this scheme, VCO at the modulator transmits a particular frequency during occurrences of bit 1 in the digital data and remains idle during occurrence of bit 0. At the demodulator end, presence or absence of the frequency is tracked by the PLL. PC output followed by LPF represents demodulated signal, which is equivalent of original digital information.

For this scheme, VCOIN < 0.6V for logic 0 and

VCOIN close to 0.9*VCC for logic 1 is recommended.

Use of PC2 at demodulator gives good results over wide range of frequency.

Figure 7. Scheme 1

Advantages:

-  Power consumption is less at modulator.

-  A burst of frequency is transmitted only during transmission of a specific data bit (either 1 or 0), hence there is less noise created in the transmission media.

-  Single frequency is used, hence bandwidth requirement is lesser.

-  Gives better performance even at higher frequencies (200kps or higher) of modulating signal (as compared to scheme 2), because of wide separation possible between logic 0 and logic 1 voltages.

Limitations:

-  It is difficult to make out if remote modulator is defunct.

-  When VCOIN < 0.6V (logic 0), modulator output may either be 0V or VCC, however this does not affect demodulation.

5.2  Scheme 2:

In this scheme, VCO at the modulator transmits one particular frequency during occurrences of bit 1 in the digital data and other frequency during occurrence of bit 0. At the demodulator end, change in the frequency is tracked by the PLL. PC output followed by LPF represents demodulated signal, which is equivalent of original digital information.

For this scheme, 1.0V < VCOIN < 0.9VCC is required.

Use of PC2 at demodulator gives good results over wide range of frequency.

Figure 8. Scheme 2

Level shifting of input digital signal is required to meet VCOIN input range, which can be achieved using level shifter circuit,

Figure 9. Level shifter circuit using LP211

As can be seen from the test waveform above, a digital signal Vin (0V-3.3V) is converted to VCOin (1.07V-4.5V).

Advantages:

-  It is easy to make out if remote modulator is defunct.

Limitations

-  Power consumption is more at modulator due to continuous oscillations

-  Requires more bandwidth

-  As VCOIN logic 0 and logic1 voltage level separation decreases, noise on demodulated output increases

6.  Conclusion

This application report described logic level implementation of BFSK modulator and demodulator using HC/HCT4046A devices.

However, while implementing this circuit for a real time application, following are some of the important factors to consider for reliable communication link,

(i)  output impedance of the modulator,

(ii)  characteristic impedance of the transmission media,

(iii)  frequency response of transmission media,

(iv)  input impedance of the demodulator.

Hence, impedance matching and signal conditioning becomes an important part in a practical system.

Implementation of FSK modulationPage 15