EE 501 Lab 9 Push Pull Output Stage

Objective:

·  To understand the push pull circuit.

·  To simulate push pull output stage with low supply voltage, and implement it with constant gm input stage to get a full version for 2nd project.

Tasks:

Floating class AB op amp is sent along this email.

In this lab, we will use supply voltage of 2.2V.

A simple push pull stage as an example is shown in figure below. Both M1 and M2 ACT AS COMMON SOURCE AMPLIFERS. When designed properly, this circuit can sink and source equal amounts of current. Therefore, push pull stage amplifier is very popular as an output amplifier stage.

To obtain output at midpoint of the supply voltage, a configuration as follows can be used to adjust the voltage.

Push pull is usually defined as class AB amplifier, for the reason that M1(or M2) conducts half of the input sine wave cycle, and also conducts a small amount of the other half. This configuration minimizes t he quiescent power dissipation and is power efficient.

In this lab, we will try to implement class AB floating gate amplifier, as shown in figure below. The file will be given with email.

To assure self robust, the current through two channels and the current through corresponding bias path need to be matched with certain ratio. Also, the transistors in circles need to be matched with ratios. This will assure equal current source and sink ability for the output stage.

Plot below is the simulated current from original class-AB opamp sent with email. X axis is the differential input voltage. The two current through floating class AB control is not balanced at 0 input voltage. Try to make the two current balanced, and see how the output voltage looks. Compare it with single common source amplifier output stage.

The push pull output stage realizes that linear output voltage of the amplifier is extended to 100mV from rail, as shown follows. There is an offset at the output, which due to the unbalanced source and sink ability of two output common source transistors (N and P). Also note that two output common source transistors can’t perfectly make the output rail to rail, since once the Vds goes below Veb, transistor goes to triode. So make Veb low is also important.

Phase and gain is plotted also, which can be further optimized.