A Simple Processor Model for Teaching Microcode

A Simple Processor Model for Teaching Microcode

Kenneth A. Williams

Computer Science department

North Carolina A&T State University

Abstract

A simple model of a CPU control unit is presented to aid in teaching students how microcode can be used to implement a processor. This model provides students with the opportunity to write microcode by selecting the ALU function, memory operation and the connection of registers to the internal bus. Microcode programming is accomplished by checking boxes that represent bits in a microcode store. A microcode animator has been developed to illustrate the execution of the microcode and to assist the students by detecting common mistakes.

1.  Introduction

Computer Science and Computer Engineering students at North Carolina A&T State University have been successfully using a simplified model of a CPU control unit to understand microcode. This model provides the student with the opportunity to write simple microcode to define machine language instructions.

The topic of microcode can be one of the more difficult subjects in undergraduate architecture classes. Students learn best through active learning, yet the coverage of microcode in many architecture textbooks [1][2][3] does not provide the opportunity for instructive exercises. The model proposed here provides students with the ability to define microcode to implement machine language instructions. Students define the microcode by specifying the active bits in a simulated microcode store. This microcode store is visualized by a table whose columns represent bits controlling the copying of register values to and from the internal bus. Students also specify any ALU function or memory operation to be taken. Each row of the table represents a microcode step. All actions in a row are considered to occur simultaneously.

Students complete microcode assignments by checking boxes as shown in table 1. Assignments usually consist of many tables requiring the student to define several machine language instructions. Multiple tables can be printed on paper for the students to practice.

A microcode simulator or animator has been developed to allow the students to visualize the microcode and verify its action. The microcode simulator is a Java applet that runs in a web browser. The simulator has been used in lecture to demonstrate microcode execution. It is also used by the students to check the validity of their answers to homework assignments.

A major goal of the microcode model is to teach the students that computer systems are composed of many layers. Students are taught in architecture and digital logic courses how silicon structures can create transistors, how transistors can create gates and how gates can create logic circuits. Students also learn how applications are created from high level programs which are compiled to assembler language. The microcode model attempts to span these two concepts, showing the student how logic circuits can create a CPU control unit that will implement machine language instructions. Care was taken to show how the control unit can be constructed from simple gates.

2.  Architecture

The basic architecture of the model is shown in figure 1. The model contains a small number of elements common to every processor.

Bus – The internal processor bus connects all of the other components. Only one register may copy its value to the bus at a time, although the bus value may be simultaneously copied to multiple registers.

Instruction register – This register holds the currently executing instruction. The full register may be loaded from the bus while the address field bits of the instruction can be copied to the bus.

Figure 1 – Simple CPU model

Table 1 – Microcode for subtract R1, memory[R2] instruction

bus ® IR / IRadr ®
bus / result ®
bus / bus
® ALU / bus
®
op / bus
® PC / PC ®
bus / bus
® R1 / R1 ® bus / bus
® R2 / R2 ® bus / bus
® MAR / bus
® MBR / MBR ®
bus / ALU
func / Mem
func
1 / X / X / X / inc / read
2 / X / X / wait
3 / X / X
4 / X / X
5 / X / X / add
6 / X / X / read
7 / X / X / wait
8 / X / X / sub
9 / X / X

Program counter – This register always contains the address of the next instruction to be executed.

User registers – Two user registers are used in the model. The microcode provides separate controls to load and store these registers.

ALU – The Arithmetic Logic Unit performs all arithmetic and logic functions. Since the microcode is usually independent of the exact arithmetic or logic function executed, the simulator supports only add, subtract, increment and decrement. The ALU input for increment and decrement come from the bus while the second operand for other arithmetic functions comes from the operand register. The result of any ALU operation is stored in the result register.

Operand register – This register provides input to the ALU for arithmetic functions that require two operands. It must be loaded previous to executing a function in the ALU.

Result register – This register receives the results of any ALU calculation.

Memory Address Register – The memory address register (MAR) must be loaded with the address of any memory location that is to be read or written.

Memory Buffer Register – Any value read from memory will appear in the memory data register (MBR). The MBR must be loaded with a value to be written to memory.

The microcode store is represented by a table with sixteen columns. The first fourteen columns control the connection of the registers to and from the bus. The last two columns define the ALU function and the memory operation to be performed. A row of the microcode table represents a single step of the microcode program. Students create a microcode program by putting an “X” in the boxes of the table indicating that that bit of the microcode store is true. A true bit will cause the value of a register to be copied to or from the internal bus during that microcode step. If the box is unmarked, the switch for that column is open and no value is transferred for that register.

In the model, the ALU performs all arithmetic, including any arithmetic needed to calculate an effective address. When required, the ALU function can be set to add, subtract, increment or decrement. The switch copying the bus value to the ALU must be set to true when any ALU operation is performed. For simplicity, all ALU operations are assumed to complete in one microcode step.

The interface to the system RAM is through the memory address register and memory buffer register. To read data or an instruction from memory, the memory address must be placed in the MAR and the memory control set to read. To write data, the address must be copied to the MAR, the data to the MBR and the memory control set to write. Memory reads and writes are assumed to be much slower than microcode steps. The CPU must issue a memory wait before any value read from memory is available in the MBR. The memory wait function stops the execution of microcode steps until the previous memory operation is complete. Memory operations are assumed to occur at the end of a microcode step. Thus a read command can be sent to the memory during the same microcode step that copies the address into the MAR.

3.  Microcode example

Microcode programs implement the standard fetch execute cycle of a) fetch the instruction from memory, b) increment the program counter, c) fetch the operand, d) execute the operation and e) write back the results. The instruction decode step, which is usually included in the fetch execute cycle, is omitted because it does not involve any microcode steps. Table 1 illustrates the microcode to implement a subtract instruction using an index register. The first three lines implement the instruction fetch and program counter incrementation. Step 1 copies the address in the program counter register to the bus, where it is then copied into the MAR. The memory function is set to read to get the next instruction from memory. While the program counter address is on the bus, it is also brought into the ALU, where it is incremented. In step 2, the incremented address is copied from the result register and back to the program counter. At the end of step 2, the microcode will wait until the previous memory operation, the read of the instruction, is complete. The instruction is then copied from the MBR across the bus and into the instruction register. To compute the effective address of the memory operand for the operand fetch, the address field of the instruction must be added to the value in the index register, R2. In step 4, the value in user register R2 is copied into the operand register. In the next step, the value of the address field of the instruction is copied onto the bus and then brought into the ALU to be added to the value in the operand register. The sum is stored in the result register. This effective address is copied to the bus in step 6 and into the MAR. The microcode starts the read of the data operand from memory. In step 7, the value in R1 is copied to the operand register in preparation for the later subtract. Before step 8 can be executed, the microcode will have to wait for the read of the data operand to complete. Once available, the data in the MBR is copied to the ALU, where it is subtracted from the R1 value in the operand register. In the final write back step, the result is copied to register R1.

Students can check their microcode programs using the microcode animator. As they step through a microcode program, the activated switches change color and form, showing where the data is flowing. The microcode animator also checks the microcode programs for common mistakes. Some of the mistakes detected by the animator include copying the values of two different registers to the bus in the same step, copying a value from the bus without copying another register’s value to the bus, failing to wait for a memory operation to complete, and performing an ALU operation without copying a value into the ALU.

Many different machine language instructions can be implemented with the microcode model, providing the instructor with a range of possible assignments. Defining the microcode for an instruction ensures that the student understands how the machine language instruction actually works. For arithmetic instructions, different addressing modes require different microcode. The model can easily implement jump or branch instructions, including function call and return.

4.  Simplicity of design

Writing a microcode program for the simple CPU model only requires that students mark an “X” in the appropriate columns and select the necessary ALU and memory functions. This method was chosen in preference to a register transfer notation because of its simplicity. Hardware definition languages have an advantage in flexibility, power and correspondence to real world hardware design [4]. The complexity and requirements of syntax can distract some students from the goal of understanding microcode-based control units. The execution of table-based microcode can be easily explained at the gate level. Each column of the microcode represents a switch that connects a register to the internal bus. Connections going from a register to the bus are realized by a transistor switch. A true value in a microcode column that connects the bus to a register activates the clock input of the flip-flops used to construct the register.

This microcode model omits certain features normally found in a real system. The model does not support microcode branching or the concept of microcode functions. All microcode programs execute sequentially from line to line. The two user registers are handled individually, which hides the commonality between instructions. Thus the microcode for an Add to R1 machine instruction is different from the microcode for an Add to R2 instruction. These simplifications make it easier for the student to grasp the concept of microcode before moving on to more complex systems.

5.  Extensions

The CPU model is intentionally simple, allowing the students to consider improvements and enhancements as further topics are introduced. Extensions often discussed in the lecture include:

Multiple registers – The model only contains two user registers, which are accessed separately by the microcode. The model can be easily enhanced to include a register field in the instruction that connects to a demultiplexor whose outputs select the specific register to be accessed. The microcode instructions for each register are then replaced with a single microcode instruction that acts upon the selected register.

Multiple busses – When instruction pipelining is discussed, enhancements to the simple microcode processor are considered that might support pipelining. Because the result write back phase of the instruction cycle often involved copying the result register to a user register, an additional bus connecting the result register to the user registers allows this stage to overlap with reading the next instruction from memory.

Separate data and instruction memory – When pipeline hazards are discussed, the model can be modified to provide two MAR and two MBR registers, one for instruction memory and the other for data memory.

Constant registers – When discussing interrupts, the model is expanded to include registers which hold constants such as the address of the new program counter when an interrupt occurs.