Using Verilog to Build memory interface in NorthBridge
Tien-Hsiang Lo
Computer Engineering
Florida Institute of Technology
Abstract
SRAM shorted for static random access memory and pronounced s-ram. SRAM is a type of memory that is faster and more reliable than the more common DRAM (dynamic-RAM). DRAM stood for dynamic random access memory, a type of memory used in most personal computers. DRAM dataresides in a cell made of a capacitor and a transistor.Northbridge provide an interface between devices and CPU or memory in PC system.System can access data more effectively if there is a good memory interface in Northbridge.
Introduction
In the small research, I built three portions using Verilog. The first one shows how to access RAM, and the second is synchronous RAM, the third isthe only shell that instantiate the major files: access_ram.v(control), and the sync_2psram.v(ram_model).
PCArchitecture
There is SRAM within CPU, Graphic chip and even memory. Although it has itself controller, Northbridge still has to provide an ideal interface.
Verilog code
I use the same time scale in bothaccess_ram.v and sync_2psram.v.
Access Ram
It generates the RSTJ, WCLK, RCLK.
`timescale 1ns/10ps //time units/precision
module access_ram( RADDR, RCLK, RDATA, RENJ, WADDR, WCEJ, WCLK, WDATA );
output [2:0] RADDR;
output RCLK;
input [31:0] RDATA;
output RENJ;
output [2:0] WADDR;
output WCEJ, WCLK;
output [31:0] WDATA;
reg RSTJ;
reg [3:0] counter;
reg ck;
reg wej;
reg rej;
reg [31:0] dout;
parameter udly = 1;
/* --- Place Module Definition Here --- */
initial begin
RSTJ = 1'b0;
RSTJ = #23 1'b1;
ck = 1'b0;
forever #10 ck = ~ck;
end
assign WCEJ = wej;
assign RENJ = rej;
assign WDATA = dout;
assign WADDR = counter[2:0];
assign RADDR = counter[2:0];
assign WCLK = ck;
assign RCLK = ck;
always @(posedge ck or negedge RSTJ)
if (!RSTJ)
counter <= #udly 4'h0;
else if ((!wej) || (!rej))
counter <= #udly counter + 1'h1;
always @(posedge ck or negedge RSTJ)
if (!RSTJ)
wej <= #udly 1'b1;
else if (counter==4'h0)
wej <= #udly 1'b0;
else if (counter==4'h7)
wej <= #udly 1'b1;
always @(posedge ck or negedge RSTJ)
if (!RSTJ)
rej <= #udly 1'b1;
else if (counter==4'h7)
rej <= #udly 1'b0;
else if (counter==4'hf)
rej <= #udly 1'b1;
always @(counter[2:0])
case(counter[2:0])
3'h0 : dout = 32'h00000000;
3'h1 : dout = 32'h11111111;
3'h2 : dout = 32'h22222222;
3'h3 : dout = 32'h33333333;
3'h4 : dout = 32'h44444444;
3'h5 : dout = 32'h55555555;
3'h6 : dout = 32'h66666666;
3'h7 : dout = 32'h77777777;
endcase
//$display($time,,"...... end now...... ");
//$display($time,,"...... end now ...... ");
// $finish(1);
endmodule // acess_ram
sync_2psram.v
1. WCEJ : It is low active write enable at the rising edge of WCLK.If WCEJ is low, then the ram_model will save the value presentin WDATA[31:0] to where the WADDR[2:0] is indicated. for example: at the rising edge of WCLK if the WADDR[2:0] == 011, and the WDATA== 32'h3333_3333, then the ram_model will save 32'h3333_3333to the 4thbuffer in it.Actually ,there are 8 buffers, coordinate to the WADDR: 000,001,010,011 ~ 111.
2. WADDR : select the number of buffer whichyou want to save data.
3. WDATA : the data whichbe saved.
4. RENJ:It is low active read enable, at the rising edge of RCLK, if the RENJ is low and the RADDR== 010 , then the ram_model will put the datawhich was already in its inner 3th buffer to RDATA at next CLOCK period.After the rising edge that RENJ was sampled, the data will present at RDATA bus, and then you can latch it at next rising of RCLK.
`timescale 1ns/10ps
module sync_2psram(RADDR,RENJ,RCLK,WADDR,WCEJ,WCLK,WDATA,RDATA);
input [2:0] RADDR;
input RENJ;
input RCLK;
input [2:0] WADDR;
input WCEJ;
input WCLK;
input [31:0] WDATA;
output [31:0] RDATA;
parameter udly = 1;
reg [31:0] databuf [0:7];
reg [2:0] rdec;
reg [31:0] d0,d1,d2,d3;
reg [31:0] d4,d5,d6,d7;
reg [31:0] RDATA;
/***************************************************************************sram for data through freq infx from WCLK domain to RCLK domain*********************************************************************/
always @(posedge WCLK)
if (!WCEJ) begin
databuf[WADDR] = WDATA;
end
always @(posedge RCLK )
if (!RENJ)
RDATA <= databuf[RADDR];
//rdec = RADDR;
/**************************************************************************/endmodule
top_ram.v
It isthe only shell that instantiate the major files: access_ram.v(control), and the sync_2psram.v(ram_model).
module top_ram;
wire [2:0] RADDR;
wire [31:0] RDATA;
wire [31:0] WDATA;
wire [2:0] WADDR;
wire WCEJ;
wire WCLK;
wire RCLK;
wire RENJ;
acess_ram I_7 ( .RADDR(RADDR[2:0]), .RCLK(RCLK), .RDATA(RDATA[31:0]),
.RENJ(RENJ), .WADDR(WADDR[2:0]), .WCEJ(WCEJ), .WCLK(WCLK),.WDATA(WDATA[31:0]) );
sync_2psramI_6( .RADDR(RADDR[2:0]), .RCLK(RCLK), .RDATA(RDATA[31:0]), .RENJ(RENJ), .WADDR(WADDR[2:0]), .WCEJ(WCEJ), .WCLK(WCLK),.WDATA(WDATA[31:0]) );
endmodule // top_ram
Conclusion
The term static is derived from the fact that it doesn't need to be refreshed like DRAM. While DRAM supports access times of about 60 nanoseconds, SRAM can give access times as fast as 1 nanoseconds. In addition, its cycle time is much shorter than that of DRAM because it does not need to pause between accesses.
I found that Acer Labs Inc. use very similarkernel code to access RAM. OEM Company can modify registry to access different type or speed RAM. The Engineers explained that they have to combine other graphic chip to produce a new Northbridge for laptop. Combo Chip can save more cost and area.
Unfortunately, I don’t have more reference to explain how to build the whole interface between Northbridge and RAM.
Reference
Acer Labs Inc., M1681P4 SuperNorthBridge –CPU, AGP, HTT andMemory Controller, V0.92, March, 2003.
Acer Labs Inc., M1681 Source code by VHDL
Altera,QDR SRAM Controller, V3.0, February, 2003
Xilinx, Spartan-II Family as a Memory Controllerfor QDR-SRAMs, WP111 (v1.0) February, 2000