1)True/false (1 pt each)

  1. T / F The energy per N-bit conversion for a cyclic ADC is proportional to the number of bits, N.
  2. T / F When limited by component matching, SARs scale in area as roughly 2N in order to maintain a constant DNL in LSBs.
  3. T / F OTAs, in general, are slower than true op-amps because of their higher output impedance.
  4. T / F In a cyclic ADC, if I am suffering from DC offsets in the comparator, I can fix this by increasing the gain on the residue to be more than 2.
  5. T / F The difference between chopping and dynamic element matching is that chopping is applied to the signal itself, whereas dynamic element matching is only applied to certain components’ DC bias.
  6. T / F Any feedback system with 3 or more poles is unstable
  7. T / F Input referred noise density in BJTs and MOSFETs is proportional to 1/gm
  8. T / F Op-amps are most stable in unity-gain feedback because that’s when closed-loop gain is lowest.
  9. T / F Large area transistors have worse flicker noise because a large gate contains more traps.
  10. T / F The gm of bias transistors in an amplifier should be minimized for low noise.
  11. T / F The gm of amplifier input transistors should be minimized to reduce noise.
  12. T / F Poles in feedback provide LHP zeros in a closed loop transfer function, but still degrade stability.

2)Multiple choice: Circle the correct answer (1 pt each).

  1. Which of the following classes of ADC would not be appropriate for applications where many different signals are multiplexed through the same ADC (like an image sensor)?

SARsigma-delta cyclicpipeline

  1. Which of the following techniques is least effective in reducing DC offsets and flicker noise?

Choppingmaking transistors HUGE

reducing VOD for higher gmcorrelated double-sampling

3)(4 pts) Your company has a successful 60GS/s, 4-bit flash ADC for wireline communications. It has an ENOB of 3.9 bits when converting full-amplitude signals with a Bandwidth of 30GHz. However, a new communication standard comes out, requiring greater resolution. To meet this, your group develops a new 6-bit ADC by simply quadrupling the number of comparators (and generating 4 times as many levels). In tests running at 100MS/s it shows the expected improved resolution (ENOB = 5.8bits), but at 60GS/s, with 30GHz bandwidth, full amplitude signals, it’s ENOB is only 4.1dB. The system designer claims the problem is the comparators: he says they don’t settle fast enough to provide the required resolution. The engineer who designed the comparators disagrees. She says the comparators have plenty of margin, but the system designer failed to scale up the clock drivers when he quadrupled the number of comparators. Devise a simple test for the new ADC to distinguish between these cases. 2-3 Sentences:

4)(8pts) Your friend in AEP has developed an ultra-dense, ultra linear, ultra-precise capacitor, but which has the problem of having a large back-side parasitic. He wants to demonstrate it in a simple switched-capacitor circuit. He brings you the following 4 designs and asks which is best. Rank them in order (1=best, 4=worst) and give reasons for your ordering in terms of noise, gain accuracy and settling time. Assume all designs use the same CMOS-based OTAs and switches, and that the thick plate of each capacitor is the backside with a large capacitance to ground.

5)Consider the gmC filter shown below

  1. (4pts)You want to implement a band-pass filter with the following specs:

Center frequency wc=100MHz, BW=20MHz, in-band ripple<2dB, rejection>20dB for f<30MHz, f>330MHz. You want something in the form:

Find the coefficients:

  1. (5pts)For the gm-C filter shown, which output can give you the transfer function you need, and write that transfer function for that output terms of gm0-gm4 and C. (Hint, if you aren’t sure, write Vout2-Vout4 in terms of Vout1, then solve for Vout1 in terms of Vin, and so Vout2-Vout4 in terms of Vin)

Which one?______

______

  1. (4pts ) Choose the ratios gm1/gm0, gm2/gm0, gm3/gm0 and gm4/gm0 so that the filter from part b meets the specs from part a.

gm1/gm0=______, gm2/gm0=______,gm3/gm0=______,gm4/gm0=______,

6)For the 2-stage amplifier shown above

  1. List all of the components that are part of each listed function (5pts):

Differential pair:______

Passive current mirror:______

Active current mirror:______

Positive feedback:______

Reset switch: ______

Digital control switch: ______

Common-mode feedback: ______

Also list which broader function each component is part of:

DAC:______

Amplifier:______

Comparator:______

  1. (4pts)The core amplifier (excluding comparator and DAC) is constructed from unit NFETs (VOD=200mV for Id=20uA so gm=0.2mS), PFETS, (VOD=400mV for Id=20uA so gm=0.1mS) and unit resistors (R=5k). Assume all transistors have VTH=500mV. All of these unit cells have the same physical area. Using a lego-style design approach, choose multipliers, N1 and N2 and R1 and R2 (both integer multiple of 5kΩ) each device, so that the two stages have the same gain, the total gain is 900 (~60dB), and the area and power are reasonably minimized (e.g. don’t be dumb). Ensure the transistors all stay in the desired operating regime, and the input referred noise is <8nV/Hz½ . Ibias=20uA. No points will be docked for mild over-design if your numbers are nice.

State the multipliers for each of the following (ignore the inputs from the current DACs):

N!=______, N2=______, R1=______, R2=______

  1. (5pts) Assuming threshold mismatch for both NFETs and PFETs of VTH=4mV, and assuming N1=16, and N2=1 (not the right answers for part b) and ignoring all other forms of mismatch, what is the (approximate) expected 1- input referred DC offset of the amplifier? What is the probability of the amplifier being saturated due to DC offset (which here means exceeding 1V differential) Start by stating which devices you can ignore, (from M2-M12) and why. For ease of estimation of P, in a Gaussian distribution:

P(|V|>1)~30%, P(|V|>2)~5%, P(|V|>3)~0.3%,

Ignore:______

Voff_input=______P(Vout1V)~______

For parts d-e assume N1=15, that R1=R2=10k, and that N2=1, while R3=R4=150k (Ibias is still 20uA)

  1. (2 pts)The function of the offset correction current DAC is to cancel the effect of a 3- DC offset. You can treat this as equivalent to injecting an intentional input dc offset, so as to suppress the offset from mismatch. Start by computing I1 and I2 in terms of Ibias, M (the multiplicity of M21) and B0, B1, B2 and B3.

I1=______, I2=______

  1. (4pts) Now, what are the minimum and maximum input-referred offsets achievable (ie for B0-B3=0000 and 1111), in terms of M, the multiplier on the current-DAC’s reference device? What is the resolution on this input-referred offset correction (ie what is VLSBof the input-referred offset) Hint: Vx1-Vx2 =( I1-I2)*(R1+R2)/2

Voff(0000)=______Voff(1111)=______VLSB=______

  1. (4pts) Assume the 1- DC offset of the amplifier is 0.5mV (not the right answer to part c). Choose the multiplicity of M21, M, so that the DAC has the finest resolution possible while still successfully cancelling the ±3- cases. Assuming B0-B3 are chosen to optimally suppress the mismatch-induced input referred offset (for offset <3-) what is the worst-case residual DC offset on the output?

Multiplicity of M21:M= ______

Residual dc offset: ______

  1. (6pts)In order to find the optimal DAC bits, an SAR is engaged. For this part, assume M=25. For an example case, where Voffset=1.5mV, equivalent to Vin1-Vin2=1.5mV, Write an equation for Vout in terms of Voffset, B0, B1, B2 and B3, walk through the SAR algorithm keeping track of B0-B3, Vx and Vout. Note that the comparator is essentially measuring the sign of Vout.

Vout (Voffset, B0, B1, B2, B3)=______

iteration # / 1 / 2 / 3 / 4 / final
B3 / 0 / 1
B2 / 0 / 0 / 1
B1 / 0 / 0 / 0 / 1
B0 / 0 / 0 / 0 / 0 / 1
Vout

7)

: Consider the circuit shown (note during phase 1, the OTA’s have their Common mode set.

  1. (4pts) Based on the structure shown, redraw the above circuit as a block diagram of made up of time delays, adders, integrators
  1. (4pts) What is the z-domain transfer function of this circuit?

Vout(z)/Vin(z)=______

  1. (4pts) Draw the poles and zeros on the z-plane.
  1. (4pts) Sketch the magnitude response of this filter across frequency for ω from 0 to ωclk/2.

8)A different style of ADC: in applications where high resolution, low sample-rate analog to digital conversion is needed for a large number of parallel signals, a structure called a “ramp converter” is sometimes used. A ramp ADC consists of two shared components: an analog ramp generator (output Vramp) and N-bit digital counter (outputs B0-BN-1). The ramp, digital bits, and clock of the counter are then distributed to M unit ADCs, each of which consist of a comparator and N-bit latch, clocked by the comparator. When Vramp passes the input voltage of a given comparator, the present count state is latched in for that unit ADC.

a)(2pts) Assuming the ramp goes from 0 V to 2V, what is the resolution (VLSB) of the converter, in terms of N?

VLSB=______

b)(2pts) Assume the comparators are guaranteed (for |Vin-Vramp|>VLSB/2) to settle in time Tcomp, what will be the sample rate of the ADC in terms of N, Tcomp?

Fs=______

c)(2pts) What do you expect to dominate INL in this ramp ADC, and how would you improve it (2 sentences)

d)(5 pts) One effect that may be seen in large ramp ADCs (both M and N large) is a cross-talk effect where when one comparator triggers, it prevents other comparators from also triggering, even if their inputs are different by less than 1 LSB. Explain this effect in terms of the ramp capacitor and sizing of comparator inputs, and make a quantitative prediction about how Cramp must be sized relative to CGS+CGD and N to ensure this cross-talk is kept to 1 LSB or less.

e)(5pts) Suggest (and draw) a comparator that would mitigate this clustering effect.

9)Switched-cap calibrated comparator. Assume the NFETs have gm=1mS, PFETs have gm=0.5mS and the parasitic capacitance on V3 and V4 is 10fF. VTH=0.5V, VOD=200mV Vref=400mV, and VDD=2V.

  1. (5pts) During the reset phase, what will the following voltages be, assuming the system has fully settled?

V1=______, V2=______, V3=______, V4=______, V5=______

  1. (3pts) After a complete reset, the comparator switches to the read phase, and Vin=405mV. What are V1 and V2? What will the output be?

V1=______, V2=______, Vout=______

  1. (3pts) For an otherwise identical situation, the NFETs have a threshold mismatch VTHM1-VTHM2=10mV. Will the output be different? ( Y / N ) Why/why not? (1-2 sentences)
  1. (5pts) If, at the end of the read phase, |V3-V4| = 1V, how long does the reset phase have to last to have a residual offset of 1mV? (hint: ln(1000) ~ 7)

10)The circuit shown acts as a sigma-delta Buck converter. L = 100nH, C=1nF, ωclk=2Grad/s

  1. (3pts) Compute the locations of the poles of F(s) in the s-domain and plot them.

Poles: ______(s-domain)

  1. (5pts) Now, sketch the location of poles and zeros of full system, with the loop open, on the z-plane. Based on this, estimate the locations of the LC poles in the z-domain

Poles: ______(z-domain)

  1. (4pts) Draw the system diagram in the z-domain, treating the comparator as having finite gain A and added quantization noise Vn.
  1. (4pts) Sketch the expected quantization noise spectrum at the digital node VD, and on the analog output Vout.