ECE 491

Laboratory 2 – Sequential FPGA Design with Verilog

September 6, 2004

Goals

  1. To review the use of Verilog for sequential logic design.
  2. To review the use of parameterized modules in Verilog.
  3. To gain experience with using Testbenches to verify Verilog modules.
  4. To create a sequential digital system design using the S3 FPGA Board.

Background

Parameters are a useful design feature because they allow Verilog modules to be re-used with different characteristics. In this laboratory you will create a counter module that is parameterized by bitwidth and counting modulus and use several instances of this module (along with some other hardware) to create a digital clock on the S3 board.

Preparation

  1. Using the counter example in the notes as a starting point, create a parameterized counter module with two parameters: BW, the bitwidth of the counter, and M, the modulus of the counter i.e. the number of cycles the counter goes through between 0 and its highest value M-1. Note that for the counter to operate properly, the following condition must apply: M<2BW (assume in your Verilog code that this condition is met).
  1. Modify the counter testbench discussed in class to test several different instances of the parameterized counter with varying bitwidth and modulus.
  2. Write code that instantiates three generic counters to divide a 50MHz clock and use the carry outputs to generate enable signals with frequencies 1MHz, 1Khz, and 1Hz as discussed in class. The clock input of all counters should be connected to the main 50MHz clock signal.
  3. Write code that instantiates the generic counter to generate an enable signal that is true once every minute.
  4. Draw a schematic diagram of a digital clock with the interface shown below. When no button is pressed, the clock should display the current time and update every minute (we want this clock to be right more than twice a day!). If the "hr_set" button is pressed, the current time should be advanced one hour for every second the button is pressed. Similarly, "min_set" should advance the minutes of the current time. Finally, the pressing the "reset" input should set the current time to 12:00.
  5. Design Verilog code that will time-multiplex the inputs of the seven-segment display using the 1 KHz signal generated to change the display from one digit to another. You can implement this circuit as a FSM or as a counter that drives a decoder and multiplexer.

In the Lab

As you develop designs for this experiment, jot down key design decisions, rough diagrams, etc. in you laboratory notebook. Also not any problems you encounter and any observations requested by the experiment.

  1. Enter your code for the modified counter into the ISE software using Project Navigator.
  2. Enter your code for the counter testbench into ISE using the Project Navigator. Be sure to specify when adding it to the project that it is a testbench file.
  3. Click on the testbench file in the upper-left panel of the Project Navigator. Next, in the lower-left hand panel, double-click "Simulate Behavioral Model".
  4. Fix any errors which occur when you try to simulate. Verify that the testbench correctly simulates with different parameter values and print the resulting timing diagrams.
  5. Add the Verilog code to your project to implement the clock divider counters and test it by downloading it on to the S3 board. Make sure to include the constraints file "s3board.ucf" and edit it to include the ports you are using and the clock constraint.
  6. Add the Verilog code to implement your digital clock to your project and test it by downloading it to the S3 board. Make sure to include the constraint file here, too.

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