ECE 467

PROJECT REPORT

Design, Layout and Simulation

Of a Universal 4-bit shift register

Using the standard 0.25 micron CMOS technology

TEAM

VISHAL GUNTUR

UIN: 675395778

NISHA JOSHI

UIN:677316512

VARUN TURLAPATI

UIN: 658697006

Objective:

The primary objective is to minimize the propagation delay of the worst case transition of the circuit.

Selection of schematic:

LAYOUT:

DRC:

EXTRACT:

Once the DRC for the final layout is done, the next step is the Extraction. Here the software extracts the electrically important parts of the layout and eliminates unnecessary components that were placed to satisfy the design criteria.

LVS:

Now for LVS, which stands for Layout versus Schematic the software performs a complex set of compilations and comparisons of all the Components, Nets, Terminals and Nodes of both schematic and layout. These comparisons are done following the rules described in the corresponding rules library. Any mismatch found during the comparison is listed in the LVS output window.

There is a detailed classification criteria for the errors that are spotted during the LVS. They are divided into classes like Bad Device(devbad), Bad Terminals(termbad), Mergednets, Prunednets, Rewiring, Size errors. Once, we take note of the error that’s existent, we can over-come it by careful design alterations.

Problems Faced and Resolved:

During the design and execution of this lab, many errors were faced and resolved which resulted in better understanding of the software. The following are some of the problems that I found worth mentioning.

  • Bulk Nodes:

For the successful implementation of the selected logic no VDD is required. However, to simulate successfully, it was required that we place a dummy VDD to overcome an error which was named as the progn(bn). Upon, careful observation, it was noticed that the 4 terminal devices like PMOS, NMOS require the existence of a terminal which is designated as the bulk node terminal as per the CDF parameters. So, we place the dummy VDD as mentioned above.

  • Off Grid Error:

This error arises mainly due to the fact that the components are not aligned to integer coordinates. This error can be avoided by placing 1 in the snap columns provided in the display tab of options menu, instead of 0.1.

  • Merged Nets:

This problem arises when we fail to place a required via or a short metal interconnect. This problem can be avoided by careful design practices.

  • Pin placed on a Net with different name:

This is one of the errors that we faced when more than one pin was placed on the same net causing confusion on name allocation for the net.

STATISTICS:

Simulation Results:

  • Area of the layout

Area of the layout = 2073.90*3124.30*0.05um*0.05um

=16198.714 (uM) 2

  • Propagation delay:

Low to High Propagation delay: 18.03 ns

High to Low Propagation delay: 12.523ns

Total Propagation Delay = 15.27ns

  • Area and Delay Product

Area * Propagation Delay= 16198.714*15.27(uM) 2(ns)

=247354.3628(uM) 2 (ns)

Q= Area * (Propagation Delay) 2

= 16198.714*15.27*15.27(uM) 2 (ns) 2

= 3777101.12(uM) 2 (ns) 2

The device parameters that were used to achieve the above mentioned results are as follows:

PMOS: W=3uM L=250nM

NMOS: W=1uM L=250nM

C0= 10f F

However in this design we need to measure the Tplh and Tphl values to get the propagation delay at preset conditions namely Tplh is to be measured when 2 inputs are high and the third goes to high along with them and Tphl is to be measured when 3 inputs are high and one of them dies out. To attain these combinations with appropriate delay values we need to have 2 sets of delays for the sources available.

Result:

The Universal 4-bit Shift Register has been designed and the layout is constructed.

The propagation delay is 15.27ns and the area of the layout is 16198.714 (uM) 2

The Q obtained is 3777101.12(uM) 2 (ns) 2