MMVD 204 Verilog - Hardware Des-cription Language
Instructions: There shall be eight questions in total, two from each unit. Students are required to attempt five questions, selecting at least one from each unit. All questions will carry equal marks.
Maximum Marks: 60, Time = 3 hours
Internal Assessment: 40 Marks
Unit I
Verilog: Overview of Digital Design with Verilog HDL, Concepts of CPLD and FPGA, Hierarchical Modeling, Basics of Verilog - Data Types, System Tasks and Compiler Directives, Modules and Ports, Gate Level Modeling- Gate Types, Gate Delays.
Unit II
Behavioral Modeling - Structured Procedures, Procedural Assignments, Timing Controls, Conditional Statements, Multiway Branching, Loops, Sequential and Parallel Blocks, Tasks and Functions – Exercises. FSM based HDL design-Moore & Mealy machines.
Unit III
Useful modeling techniques- Procedural continuous assignments, overriding parameters, conditional compilation and execution, time scales, useful system tasks, Advance Verilog Topics- Timing and delays – types of delay models, path delay modeling, Timing checks, delay back-annotation, Switch level modeling – switch modeling elements, examples.
Unit IV
Logic Synthesis with Verilog HDL- What is logic synthesis, impact of logic synthesis, Verilog hdl synthesis, synthesis design flow, RTL to gates (Example, Verification of gate level net list, modeling tips for logic synthesis, examples of sequential circuit synthesis.
References:
1. Verilog HDL - Samir Palnitkar (Pearson)
2. Verilog HDL Synthesis, A Practical Primer – J Bhasker
3. Digital Design: With an Introduction to Verilog HDL - M. Morris Mano
4. Design Through Verilog HDL - B.Bala Tripura Sundari T.R. Padmanabhan
5. FSM based HDL Design –Peter Minns, lan Elliott(Wiley)
Electronic Science Department
Kururkshetra University, Kurukshetra
Lesson Plan
M.Tech. (MMVD), II sem
(wef session 2014-15)
Paper: MMVD 204 Verilog
Verilog - Hardware Description Language
Unit I
by Rakesh Singh
Syllabus:
Unit I
Verilog: Overview of Digital Design with Verilog HDL, Concepts of CPLD and FPGA, Hierarchical Modeling,
Basics of Verilog - Data Types, System Tasks and Compiler Directives, Modules and Ports,
Gate Level Modeling- Gate Types, Gate Delays.
References :
- Custom VLSI Microelectronics by Stanley L.Hurst (Prentice Hall 1992)
- Verilog HDL - Samir Palnitkar (Pearson)
- A Verilog HDl Primer - J. Bhaskar (Pearson)
- User mannuals of ACTEL, Altera and Xilinx CPLD, FPGA (online resource)
- Design Through Verilog HDL - B.Bala Tripura Sundari T.R. Padmanabhan
Abbreviations: SA: Short Answer type, LA: Long Answer type, CA: Concept based Answer Type, DP: Design Problem type ,TPS: Think Pair Share
PI: Peer Instruction.
Lesson No / Contents / Learning Objectives / References / Evaluation (Question Type)1 / VLSI Design Flow, Difference between VHDL and Verilog and other programming language like C C++. / 1. Students should be able to describe all abstraction level in VLSI Design flow.
2. Be able to understand the hierarchy in digital circuits and how it is used in design.
3. Be able to comprehend the abstraction and how it can be used in digital circuit design. / 1,2,3 / TPS,PI
Exams: SA
2 / Computer aided design / 1. Students should be able to understand the Computer aided design.
2. Be able to comprehend its use in IC design
3. Be able to comprehend the importance of CAD and CAD tools in IC design. / 1,2,3 / TPS,PI
Exams: SA
3 / Concepts of CPLD, FPGA / 1. Students should be able to visualize the role of CPLD & FPGA in IC industry
2. Be able to visualise the different structures of these devices in use today.
3. Be able to differentiate between these devices. / 1,2,3,4 / TPS,PI
Exams: SA & LA
4 / Introduction to HDLs, / 1. Students should be able to understand the need of HDLs in IC design
2. Be able to understand How the use of HDL changed the design scene in the IC industry. / 2,3,5 / TPS,PI
Exams: SA
5 / Verilog and its capabilities / 1. Students should be able to comprehend the role, features and capabilities of Verilog HDL.
2. Be able to comprehend the standards available for Verilog. / 2,3,5 / TPS,PI
Exams: SA
6 / Hierarchical Modeling Concepts: Design Methodologies, / 1. Students should be able to Understand the concept of hieracy in design.
2. Be able to understand the top – down and bottom-up approaches of digital design.
3. Be able to understand the design abstraction levels that Verilog can handle. / 2,3,5 / TPS,PI
Exams: SA, LA
7 / Modules, Instances, Components of Simulation and Test Bench. / 1. Students should be able to start the model writing in verilog
2. Be able to understand the concept of Instances of modules or components
3. Be able to visualise the simulation process and the role and need of using a test bench in simulation of digital circuits / 2,3,5 / TPS,PI
Exams: SA, LA, CA
8 / Basic Concepts: Lexical Conventions, Data
Types, / 1. Students should be able to understand the syntax of the basic notations in verilog,
2. Be able to understand the data types used in verilog. / 2,3,5 / TPS,PI
Exams: SA, LA
9 / System Tasks and Compiler Directives. Modules and Ports. / 1. Students should be able to comprehend the role and use of various system tasks and the compiler directives available in Verilog.
2. Be able to understand the use of modules and the various types of ports in different situations / 2,3,5 / TPS,PI
Exams: SA, LA, CA
10 / Gate level Modeling, Gate types, Gate delays. / 1. Students should be able to understand instantiation of Gates, Truth tables and buf/not types gates.
2. Students should be able to describe Rise ,fall and turn off delays in the gate level design
3. Students should be able to understand how to construct a verilog description from the logic diagram of ckt. / 2,3,5 / TPS,PI
Exams: SA
Unit II
Data Flow Modeling, Behavioral Modeling - Structured Procedures, Procedural Assignments, Timing Controls, Conditional Statements, Multiway Branching, Loops, Sequential and Parallel Blocks, Tasks and Functions – Exercises. FSM based HDL design-Moore & Mealy machines.
References :
- Verilog HDL - Samir Palnitkar (Pearson).
- A Verilog HDl Primer - J. Bhaskar (Pearson).
- Design Through Verilog HDL - B.Bala Tripura Sundari T.R. Padmanabhan.
Abbreviations: SA: Short Answer type, LA: Long Answer type, CA: Concept based Answer Type, DP: Design Problem type , TPS: Think Pair Share
PI: Peer Instruction.
Lesson No / Contents / Learning Objectives / References / Evaluation (Question Type)11 / Data flow modelling: continuous assignments, Delays / 1. Students Should be able to describe continuous assignment statement, Implicit continuous assignment statement.
2. Students Should be able to describe Implicit assignment delay, net declaration delay. / 1,2,3 / TPS,PI
Exams: SA
12 / Operator types Arithmetic operator,Logical operator,Shift operator. / 1 Students should be able to use expressions and operator in coding. / 1,2,3 / TPS,PI
Exams: SA,LA
13 / Conditional operator,Bitwise operator, Reduction operator,shift operator,equality operator / 1Students should be able to use expressions and operator in coding.
2. Students should be able to do modelling using different operator for the same digital ckt.
14 / Behavioral Modeling - Structured Procedures, Procedural Assignments / 1 Students should be able to explain the significance of structured procedures always and initial in behavioural modelling.
2. Students should be able to differentiate blocking and non blocking procedural assignments. / 1,2,3 / TPS,PI
Exams: SA
15 / Timing Controls, Conditional Statements / 1. Students should be able to use delay based timing control mechanism in behavioural modelling.
2. Students should be able to use regular delays, intra assignment delays and zero delay in modelling. / 1,2,3 / TPS,PI
Exams: SA
16 / Multiway Branching, Loops, Sequential and Parallel Blocks / 1. Students should be able to use conditional statements looping statement in behavioural modelling.
2. Students should be able to differentiate sequential and parallel blocks and use in behavioural modelling. / 1,2,3 / TPS,PI
Exams: SA,LA
17 / Tasks and Functions – Exercises. / 1. Students should be able to differentiate between Task and function.
2. Students should be able to use task and function in their modelling. / 1,2,3 / TPS,PI
Exams: SA
18 / FSM based HDL design-Moore & Mealy machines / 1. Students should be able to differentiate between Moore and Melay machines.
2. Students should be able to do modelling using both types of machines. / 1,2,3 / TPS,PI
Exams: SA
19 / Examples of different digital ckts using task and function and operator. / 1. Students should be able to use mixed style of modelling for different digital ckts. / 1,2,3 / TPS,PI
Exams: SA,LA
Unit III
Useful modeling techniques- Procedural continuous assignments, overriding parameters, conditional compilation and execution, time scales, useful system tasks, Advance Verilog Topics- Timing and delays – types of delay models, path delay modeling, Timing checks, delay back-annotation, Switch level modeling – switch modeling elements, examples.
References :
- Verilog HDL - Samir Palnitkar (Pearson).
- A Verilog HDl Primer - J. Bhaskar (Pearson).
- Design Through Verilog HDL - B.Bala Tripura Sundari T.R. Padmanabhan.
Abbreviations: SA: Short Answer type, LA: Long Answer type, CA: Concept based Answer Type, DP: Design Problem type , TPS: Think Pair Share
PI: Peer Instruction.
Lesson No / Contents / Learning Objectives / References / Evaluation (Question Type)20 / Useful modeling techniques- Procedural continuous assignments, overriding parameters, conditional compilation and execution, time scales, / 1.Students should be able to understand the significance of assign, deassign,force and release in modelling and debugging. / 1,2,3 / TPS,PI
Exams: SA,LA
21 / overriding parameters, conditional compilation and execution, time scales, / 1Students should be able to understand the significance of defparam statement in modelling.
2.Students should be able to use condition during compilation and execution. / 1,2,3 / TPS,PI
Exams: SA,LA
22 / Usefulsystemtasks:$fopen,$fmonitor,$fdisplay,$fclose,$write,$strobe / 1Students should be able to understand the significance of different system task $fopen,$display,$monitor,$random in modelling. / 1,2,3 / TPS,PI
Exams: SA,LA
23 / Timing and delays: types of delay models distributed delay, lumped delay,pin to pin delay. / 1 Students should be able to define delay models, distributed lumped and pin to pin delays used in verilog simulation. / 1,2,3 / TPS,PI
Exams: SA,LA
24 / Path delay modelling :specify blocks, inside
specify blocks / 1 Students should be able to set path delay in a simulation by using specify blocks.
2. Students should be able to explain parallel connection and full connection between input and output pins.
3.Students should be able to define parameters inside specify blocks by using specparam statements. / 1,2,3 / TPS,PI
Exams: SA,LA
25 / Timing checks: $setup and $hold checks, $width check and delay back annotation / 1 Students should be able to explain rise fall and turn off delays and how to set min, max and typ values. / 1,2,3 / TPS,PI
Exams: SA,LA
26 / Switch modelling elements: MOS switches, CMOS Switches, Bidirectional Switches / 1 Students should be able to describe basic mos switches nmos,pmos and cmos.
2 Students should be able to understand modelling of bidirectional pass switches / 1,2,3 / TPS,PI
Exams: SA,LA
27 / Resistive Switches, Power and ground, Delay specification on switches:mos and cmos switches. / 1 Students should be able to understand modelling of Resistive switches, power and ground.
2.Students should be able to use method to specify delay on basic Mos Switches. / 1,2,3 / TPS,PI
Exams: SA,LA
28 / Example of different digital ckts using switch. / Students should be able to do modelling of different digital ckt using switch ckt in verilog. / 1,2,3 / TPS,PI
Exams: SA,LA
Unit IV
Logic Synthesis with Verilog HDL- What is logic synthesis, impact of logic synthesis, Verilog hdl synthesis, synthesis design flow, RTL to gates (Example, Verification of gate level net list, modeling tips for logic synthesis, examples of sequential circuit synthesis
References :
- Verilog HDL - Samir Palnitkar (Pearson).
- A Verilog HDl Primer - J. Bhaskar (Pearson).
- Design Through Verilog HDL - B.Bala Tripura Sundari T.R. Padmanabhan.
Abbreviations: SA: Short Answer type, LA: Long Answer type, CA: Concept based Answer Type, DP: Design Problem type , TPS: Think Pair Share
PI: Peer Instruction.
Lesson No / Contents / Learning Objectives / References / Evaluation (Question Type)29 / What is logic synthesis ,Impact of logic synthesis / 1.Students should be able to explain logic synthesis why it is necessary and what are the benefits of logic synthesis / 1,2,3 / TPS,PI
Exams: SA,LA
30 / Verilog HDL Synthesis: verilog construct, verilog operatoers / 1.Students should be able to identify verilog hdl constructs and operator accepted in logic synthesis
2. Understand how logic synthesis tool interprets these constructs. / 1,2,3 / TPS,PI
Exams: SA,LA
31 / Synthesis Design flow: RTL to Gates, Verification of the gate level netlist / 1. Students should be able to explain a typical design flow using logic synthesis.
2. Students should be able to describe the component in logic synthesis based design flow. / 1,2,3 / TPS,PI
Exams: SA,LA
32 / Verification of the gate level netlist / 1. Students should be able to explain verification of gate level netlist produced by logic synthesis. / 1,2,3 / TPS,PI
Exams: SA,LA
33 / Modeling tips for logic synthesis / 1. Students should be able to understand techniques for writing efficient RTL descriptions. / 1,2,3 / TPS,PI
Exams: SA,LA
34 / Partitioning techniques / 1. Students should be able to describe partitioning techniques to help logic synthesis provide the optimal gate level netlist. / 1,2,3 / TPS,PI
Exams: SA,LA
35 / Example of sequential ckt synthesis / 1. Students should be able to describe combinational and sequential ckts using logic synthesis. / 1,2,3 / TPS,PI
Exams: SA,LA
36 / Examples using mixed abstraction level / 1. Students should be able to use all verilog constructs in digital ckt modelling. / 1,2,3 / TPS,PI
Exams: SA,LA