Tests of High Power Oxide Implant VCSELs
V5, Tony Weidberg, 30th April ’03.
Introduction
10 TX PCBs were received from Taiwan which contained the new high power oxide implant VCSELs. One TX gave very low coupled power and this was clearly due to a very bad alignment of the array compared to the MT guide pins so this TX was not used. Extensive analogue and digital measurements were made of the remaining 9 arrays, which all worked well.
Analogue Measurements
The first set of measurements were made using a simple passive optical probe to measure the amplitude of the optical pulses and the rise and fall times of the signals. The distribution of the amplitudes with the drive currents set at 10 mA, is shown in Figure 1 below.
Figure 1 Distribution of coupled optical power for all channels of the 9 arrays on TX PCBs with a drive current of 10 mA.
There is a very broad distribution of optical power so that although the average optical power was 989W, the distribution was so broad that 8 out of 9 TXs had one channel with an optical power below 700 W. The optical power did increase with current so the specification on the coupled power could be relaxed somewhat. However the uniformity of the coupled optical power will have to be improved in production.
The measurement of rise and fall times with the simple probe were limited by the probe so they were all redone using a fast Tektronic probe (with an optical attenuator to ensure that the signal was well below the saturation level for the probe). The distribution of rise and fall times are shown in Figure 2 and Figure 3 below. The distributions show that the rise and fall times are peaked around 1 ns and are well below 2 ns.
Figure 2 Distribution of 20%-80% rise times for all VCSEL channels driven at 10 mA.
Figure 3 Distribution of 20%-80% fall times for all VCSEL channels driven at 10 mA.
Some channels had an apparently slower rise time but the significance of this is not so obvious as the signals always had a fast component and then a slow tail as illustrated in some of the scope pictures in Figure 4 to Figure 6.below.
Figure 4 Scope picture of optical signal for fibre 4 of TD007 (rise time = 0.64 ns, fall time=0.86 ns).
Figure 5Scope picture of optical signal for fibre 10 of TD007 (rise time=1.32 ns, fall time=0.82 ns).
Figure 6Scope picture of optical signal for fibre 4 of TD001 (rise time = 1.60 ns, fall time=0.86 ns).
From the scope pictures it can be seen that all channels have a very fast component to the rise and fall time and the apparently slower rise times of some channels is due to the shape of the top of the waveform. Since the DORIC4A is ac coupled with a threshold close to 0 we might well expect that the digital performance will still be very good, even for the slower channels.
BER Scans
The central 6 channels of all 9 arrays were used to perform BER scans using a pre-series harness. All channels worked very well on all arrays. The width of the region in the timing scan which gave no errors was typically 20 or 21 ns and was never less than 19 ns. The results of the BER scans for the TTC links for each of the arrays are shown in Figure 7 to Figure 15 below.
Figure 7 TTC BER scan versus TX DAC value for TX TD000.
Figure 8TTC BER scan versus TX DAC value for TX TD001.
Figure 9TTC BER scan versus TX DAC value for TX TD002.
Figure 10TTC BER scan versus TX DAC value for TX TD003.
Figure 11TTC BER scan versus TX DAC value for TX TD004.
Figure 12TTC BER scan versus TX DAC value for TX TD005.
Figure 13TTC BER scan versus TX DAC value for TX TD006.
Figure 14TTC BER scan versus TX DAC value for TX TD007.
Figure 15TTC BER scan versus TX DAC value for TX TD009.
From these BER scans it can be seen that all the 6 channels tested work very well on each TX PCB. The turn on of the system at around a TX DAC setting of 100 corresponds to a VCSEL drive current of about 5 mA. This is above laser threshold for these arrays but corresponds to the minimum value for which the BPM-12 driver circuit gives a reasonable output signal. The channels which have non zero BER at high TX DAC values correspond to channels with a coupled power above 2 mW. The power reaching the PIN diode during ATLAS operation will be lower by about 2 dB because of the attenuation in the fibre and the extra MT connector. Therefore the error free region during ATLAS operation will be wider than seen in these scans.
Mark to Space Ratio
The mark to space ratio of the VCSEL optical needs to be close to 50:50 in order to maintain a low clock jitter. With biphase mark encoded data, the DORIC4A creates clock pulses from both edges of the 20 MHz clock. Therefore if the mark to space ratio is not equal to 50:50 there will be two “families” of recovered 40 MHz clock, one with a period shorter than 25 ns period and one with a longer period, which effectively creates jitter in the clock. The BPM-12 chip has a system for adjusting the mark to space ratio so that by setting a register the mark to space ratio can be tuned to be close to 50:50. The optimal register value to get a 50:50 mark to space ratio for the electrical output of the BPM-12 is being measured for every channel for every chip as a function of fine delay. The results for one channel are shown inFigure 16 below.
Figure 16 Optimal value of the BPM-12 mark to space register versus fine delay.
A linear fit was made to determine the intercept (ie the optimal value of the mark to space register at a fine delay of 0) and the slope (ie the change in the optimal value of the mark to space register with fine delay). The distributions of these intercepts and slopes for all channels for a batch of ~ 100 BPM-12s is shown in Figure 17 and Figure 18 below.
Figure 17 Distribution of intercepts of the linear fit of optimal mark to space register versus fine delay.
Figure 18 Distribution of slopes of the linear fit of optimal mark to space register versus fine delay.
The mean and standard deviations of the distributions of intercepts and slopes are given in Table 1 below.
Table 1 Summary of fits of optimal MSR setting versus fine delay scans.
Fitted Parameter / Mean / Standard DeviationIntercept / 13.292 / 0.294
Slope / 0.0761 / 0.0030
The mark to space ratio of the electrical output will in general be distorted by the VCSELs, therefore it is also necessary to study the mark to space ratio of the optical signal out of the TX PCBs. The positive duty cycles of the optical output of the central 6 channels for one of the TXs were measured as a function of the mark to space register (MSR) setting and the results shown in Figure 19 below. All channels show similar behaviour and the optimal value of the MSR is 17. With the MSR set to a value of 17, the positive duty cycle was measured on all channels from 7 TXs and the resulting histogram is shown in Figure 20 below.
Figure 19 Adjustment of duty cycle with the mark to space register setting.
Figure 20 Distribution of positive duty cycle for the output of all channels from 7 TXs with the MSR set to 17.
The distribution of positive duty cycles is very well peaked close to 50% showing that there is very little variation within TXs or between TXs. However it should be noted that the optimal MSR (17) for obtaining an equal mark to space ratio for the optical signal is different for that for obtaining the optimal mark to space ratio for the electrical signal (13).
Clock Jitter
The final check that the MSR is optimal is to look at the jitter of the recovered clock. This was studied for the 6 central channels of a TX by sending the optical signals to a harness and looking at the 40 MHz clocksrecovered by the PIN/DORIC4A on the doglegs. Random data was sent to each channel so that the phase of the BPM signal was changing. The clock jitter was estimated as a function of the MSR setting and shown in Figure 21 below.
Figure 21 Jitter (full width) in the recovered 40 MHz clock as a function of MSR setting for the central 6 channels of TD007. The fine delay register was set to a value of 0.
The optimal value of the MSR is 14 for 5 channels but 15 for one. This optimal value differs slightly from the value of 17 which gave the closest to 50% duty cycle for the optical signal. This could be due to the difference in the response of the DORIC4A/PIN diode compared to the Tektronix optical probe or to the details of the algorithm used in the ‘scope to determine duty cycle. In any case it is the jitter measurement of the recovered clock which defines the final system performance. The jitter was measured for the 6 central channels of another 5 TXs. The optimal value varied from TX to TX and within a TX in the range 13 to 16. If one were to chose a single value for the MSR it would be 15. The distribution of jitter for an MSR setting of 15 is shown inFigure 22below. If one uses the optimal MSR value for each channel then the jitter would be significantly improves as shown inFigure 23 below.The improvement in the jitter in using the optimised MSR setting for each channel compared to the value of 15 for all channels is summarised in below.
Table 2 Summary of jitter measurements for the recovered 40 MHz clock.
Full width jitter (ns) / MSR=15 / Optimised MSRMean value / 0.614 / 0.431
Standard deviation / 0.203 / 0.124
Maximum value / 1.08 / 0.68
From the results shown in Table 2 using an optimal MSR setting does give a significant improvement in the jitter. However even using a common value of the MSR settings for all channels gives reasonably good performance as the RMS is still typically well below 0.5 ns.
Figure 22 Distribution of the full width of the jitter of the recovered clock for a MSR setting of 15.
Figure 23Distribution of the full width of the jitter of the recovered clock for an optimised MSR setting for each channel.
In order to understand if the variation between TX channels was affected by which PIN diode/DORIC4A was used, the results for TD007 were repeated with the MT connector reversed. The results were significantly different which suggests that even if a full calibration was done for each TX channel, a final calibration would have to be done for each channel in ATLAS. This in-situ calibration could be performed using the clock/2 mode in which the ABCD chips return a 20 MHz clock to the data links. A scan of the width of the on period of this signal should show a width of 25ns for the optimal MSR setting. The measurement would then be repeated after a single “1” had been sent in order to flip the phase of the biphase mark signal. The difference between the results of the width of the scans between the two phases would then be a measure of the unequal mark to space ratio of the VCSEL signal. Therefore by adjusting the MSR until this difference was minimised the optimal MSR setting could be determined. This procedure should be evaluated now, to verify that it can correctly determine the optimal MSR setting for each channel.
Finally the value of the fine delay was changed from 0 to 85 (corresponding to the maximum useful fine delay of 25 ns) and the clock jitter was measured as a function of the MSR setting and the results shown in Figure 24below.
Figure 24 Jitter (full width) in the recovered 40 MHz clock as a function of MSR setting for the central 6 channels of TD007. The fine delay register was set to a value of 85.
From the distribution in the fitted values of the slope (see Figure 18), we would expect the optimal MSR to be increasedat a fine delay of 0 counts,by an amount 85 * 0.0761 = 6.5. Therefore the expected optimal MSR setting would be expected to be in the range 20 to 21 counts in agreement with the results shown in Figure 24.
Conclusions
The 9 TXs tested worked well and gave very good digital performance. The analogue performance in terms of rise and fall times were also very good and shows that we can keep the specifications for the 20% to 80% rise and fall times to be less than 2 ns. There was a big variation on the coupled power but this was due to known alignment problems during assembly. The alignment should be much more reliable during assembly and most channels would be expected to give greater than 1.2 mW coupled power at 10 mA. However in order to ensure a high yield, we should give a slightly lower specification for the coupled optical power which could be relaxed to be greater than 0.7 mW coupled power at a BPM DAC setting of 165 (equivalent to a drive current of 10 mA). If necessary the drive current could be increased and this would still give us about 1 mW coupled power even for the weakest channels, which would provide the required headroom for reliable long term operation.
The mark to space ratio adjustment circuitry of the BPM-12 worked well and allowed us to obtain an equal mark to space ratio for the optical output. If the optimal MSR value was used a low jitter recovered clock signals from the PIN diode/DORIC4A on the harness was obtained. There is some variation between TX channels and the PIN diode/DORIC4As. Therefore we should stop doing the full and very slow calibration of each BPM-12 chip. An in-situ calibration scheme needs to be developed. We should measure the mark to space ratio of the optical output of the TXs on a batch basis but it is not necessary to do this for every TX.
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