1.  With serial transmission signaling elements are sent down the line one at a time. Each signaling element maybe:

·  Less than one bit

·  One bit

·  More than one bit

What are the implications of each of the above bit levels?

Answer:

Less than one bit is exhibited through Manchester encoding. (DRAW FIGURE 5.5 in PAGE 139, STALLINGS)

Biphase

Manchester code

0s reprsent a transition from high to low in middle of pulse interval and 1s represents a transition

from low to high in pulse of intervals.

One bit is represented through NRZ-L (digital) and FSK (analog) examples. (DRAW FIGURE 5.5 in PAGE 139, STALLINGS)

More than one bit depicted through QPSK. (WRITE THE EQUATION OF QPSK in PAGE 145, STALLINGS)

Constellation diagram for QPSK with Gray coding. Each adjacent symbol only differs by one bit.

With four phases, QPSK can encode two bits per symbol, shown in the diagram with Gray coding to minimize the BER — twice the rate of BPSK. Analysis shows that this may be used either to double the data rate compared to a BPSK system while maintaining the bandwidth of the signal or to maintain the data-rate of BPSK but halve the bandwidth needed.

Although QPSK can be viewed as a quaternary modulation, it is easier to see it as two independently modulated quadrature carriers. With this interpretation, the even (or odd) bits are used to modulate the in-phase component of the carrier, while the odd (or even) bits are used to modulate the quadrature-phase component of the carrier. BPSK is used on both carriers and they can be independently demodulated.

2.  Data are transferred between a sender and receiver at a rate of 1Mbps. The receiver’s clock ticks 5% faster than the sender’s clock. Under this situation, what are the implications if the receiver will attempt to sample at the centre of each bit? How can you overcome any negative implication, if any?

IRA (International Reference Alphabet) characters are typically sent in 8bit units (including the parity bit). If the receiver is faster then the transmitter by 5%, the 8-bit character will be displaced by 45% and it will still be correctly sampled even though errors have occurred.

(REFER TO DRAWN DIAGRAM 6.1c)

In the example we assume 1000Kbps per second (1Mbps). Therefore each bit is

1000ms make 1second

10Kbps = 10Kbps/1000ms = 0.1 (ms)

In our example:

1000Kbps = 1Mbps

1000Kbps/1000ms = 1(ms)

Faster by 5% = 5μs per bit time.

- Receiver samples the incoming character at 95μs (based on transmitter clock – meaning Receiver thinks the Transmitter’s Clock is reading that…)

Implications:

2 errors will occur:

1) Last sampled bit is incorrectly received.

2) Framing error occurs. Bit count will be out of alignment/whack. If bit 7 is a 1 and bit 8 is a 0, bit 8 maybe mistaken for a Start Bit.

Need synchronization which incurs about say 20% overhead as we tend to use 2-3bits per character that convey no information. (Odd or Even Parity).

To avoid timing discrepancies, then we will have to rely on Synchronous Tranmission that uses a steady stream of transmission without any start or stop codes where both receiver & transmitter clocks will be synchronized first before any transmission takes place.

(REFER TO PAGE 176-177, STALLINGS)

3.  Differentiate between error-detection and error-correction. In some situations, rectifying errors using error-detection techniques have their limitations. Elaborate on this.

Error detection vs correction

Error detection

introduce redundancy into the data stream

e.g. send everything twice!

Vertical Redundancy Check

·  a.k.a. parity check, append a parity bit to data unit

·  even parity: set parity bit so that total # of 1’s in unit (including itself) is even.

·  odd parity : similar

·  detects all errors where number of erroneous bits in unit is odd (1,3,5)

·  cannot detect even numbers of errors (parity will remain correct)

Longitudinal Redundancy Check

·  2-dimensional parity check

·  parity check over a block of consecutive data units

·  each data unit contains VRC parity bit

·  append data unit containing parity bit for corresponding bit position across all data units in block

·  cannot detect even numbers of errors in corresponding positions of even numbers of data units. (e.g. units 2 and 4 both have errors in bit positions 5 and 7).

Cyclic Redundancy Check (CRC)

·  CRC bits are appended.

·  CRC value is such that combination of data and CRC bits form value divisible by “well-known” divisor (the generator polynomial).

·  if receiver gets non-zero remainder, error occurred.

·  uses modulo-2 division, subtraction, and addition

Error correction by coding (“forward”)

v introduce enough redundancy to allow correction

v

1) Stop-and-Wait ARQ

2) Go-Back-N ARQ

3) Selective-Reject ARQ

(REFER TO PAGE 201 – ERROR DETECTION and PAGE 208 – ERROR CONTROL)

4.  Explain in terms of data link control and physical layer concepts how error and flow control are accomplished in synchronous time division multiplexing.

Answer:

Synchronous TDM is a technique to divide the medium to which it is applied into time slots, which are used by multiple inputs. TDM’s focus is on the medium rather than the information, which travels on the medium. Its services should be transparent to the user. It offers no flow or error control. These must be provided on an individual-channel basis by a link control protocol.

5.  Consider a transmission system using frequency division multiplexing. What cost factors are involved in adding one more pairing of stations to the system?

Answer:

In many cases, the cost of the transmission medium is large compared to the cost of a single transmitter/receiver pair or a modulator/demodulator pair. If there is spare bandwidth, then the incremental cost of the transmission can be negligible. The new station pair is simply added to an unused sub channel. If there is no unused sub channel it may be possible to re divide the existing sub channels creating more sub channels with less bandwidth. If, on the other hand a new pair causes a complete new line to be added then the incremental cost if large indeed.