0901/159.233 Sc
MAN
Internal/Extramural
MASSEY UNIVERSITY
MANAWATU CAMPUS
EXAMINATION FOR
159.233 COMPUTER SYSTEMS
Semester One - 2009
Time allowed: THREE (3) hours
THIS IS A CLOSED BOOK EXAMINATION
ANSWER ALL QUESTIONS
SECTION A
Fourteen multi-choice questions – each worth 2 marks 28 marks
Record your answers to the questions in Section A on the Scantron Card provided.
SECTION B
Three questions – each worth 24 marks 72 marks
Write your answers to the questions in Section B in the Blue Answer Booklet provided.
Total: 100 marks
Marks for each question are shown in brackets after the question, like this [8 marks]
Note that in some of the questions in this exam, the abbreviations hi and lo may have been used to signify logic high (usually 5V) and logic low (0V) signals respectively.
Page 1 of 17
SECTION A
14 Multi-choice Questions – each worth 2 marks
1 Which of the following comments would you expect someone to make about CISC computers but not about RISC computers?
(a) They have instructions that operate only on registers, and they have a large number of registers.
(b) They have instructions that operate only on registers, and they have a small number of registers.
(c) They have instructions that operate on memory, and they have a small number of registers.
(d) They have instructions that operate on memory, and they have a large number of registers.
[2 marks]
2 In the MIPS computer, branches
(a) occur after every instruction.
(b) are conditional.
(c) should not be used as a way of loading the Program Counter with a new value.
(d) are generally only used in loops, because they are suitable for transferring control to an earlier instruction but not to a later one.
[2 marks]
3 Amdahl's Law
(a) states that parallel processing and serial processing must be implemented as separate processes if any speedup is to occur.
(b) states that the speedup from serial processing and the speedup from parallel processing have increased by 100% every 18 months since the mid-1960s.
(c) states that speedup from parallel processing is limited by the serial processing component.
(d) states that speedup from serial processing is limited by the parallel processing component.
[2 marks]
4 The "three-address architecture" of the MIPS computer
(a) is violated by multiplication instructions, which produce double-precision (64-bit) results, and therefore have 4 registers, not 3.
(b) operates directly on words in memory. It is thus inefficient and is only used rarely; most instructions operate on registers.
(c) is very confusing for postmen.
(d) is designed to suit an operator that operates on two operands and produces a result.
[2 marks]
5 2's complement numbers
(a) are a way of representing negative numbers and there is only one representation of zero.
(b) are a way of representing negative numbers, but there are two representations of zero (+0 and -0).
(c) can represent both negative and positive numbers, and there are two representations of zero (+0 and -0).
(d) can represent both negative and positive numbers, and there is only one representation of zero.
[2 marks]
6 The "Sticky Bit"
(a) is a bias that is added to negative exponents in the sign position to convert them to positive numbers so that it is easier to determine the relative magnitude of numbers.
(b) is used to produce the correct result in some calculations whose result requires rounding up, when the digit that causes the rounding has a very low precision that would normally be ignored.
(c) is always a 0, as a result of the normalisation process, and thus it is not necessary to store it.
(d) is always a 1, as a result of the normalisation process, and thus it is not necessary to store it.
[2 marks]
7 In a single-clock-cycle architecture
(a) no resources can be shared between different instruction types (e.g., calculating the address of memory reference instructions and the result of register operations).
(b) is it not possible to use a single ALU for producing the results of an R-type calculation (for an addition operation, say) and for determining the destination address of a branch instruction.
(c) no resources can be shared between the different operations that belong to an instruction.
(d) a single ALU can be used for R-type calculations (for an addition operation, say) and for calculating the address of the next instruction (when incrementing the Program Counter).
[2 marks]
8 In a microprogrammed controller
(a) the address of the next microinstruction is always calculated by a dedicated ALU and the values for the signals that are used to control the architecture are produced by a Boolean circuit, based on the address of the current microinstruction.
(b) the address of the next microinstruction is always calculated by a dedicated ALU and the values for the signals that are used to control the architecture are stored as bit values in micromemory.
(c) the address of the next microinstruction is often stored as a field in the current microinstruction, and the values for the signals that are used to control the architecture are produced by a Boolean circuit, based on the address of the current microinstruction.
(d) the address of the next microinstruction is often stored as a field in the current microinstruction, and the values for the signals that are used to control the architecture are stored as bit values in micromemory.
[2 marks]
9 In the diagram below, which represents the architecture of a pipelined MIPS computer
(a) data progresses from stage to stage through the pipeline without the need for any clocking, as the stages are designed to have the same delays, and the diagram portrays a von Neumann architecture.
(b) the paler vertical rectangles from top to bottom of the diagram represent registers between the pipeline stages, and the diagram portrays a von Neumann architecture.
(c) data progresses from stage to stage through the pipeline without the need for any clocking, as the stages are designed to have the same delays, and the diagram portrays a Harvard architecture.
(d) the paler vertical rectangles from top to bottom of the diagram represent registers between the pipeline stages, and the diagram portrays a Harvard architecture.
[2 marks]
10 In the MIPS assembler sequences shown below
(a) sequence A does not have a hazard and sequence B has a hazard.
(b) sequence A does not have a hazard and sequence B does not have a hazard.
(c) sequence A has a hazard and sequence B has a hazard.
(d) sequence A has a hazard and sequence B does not have a hazard.
[2 marks]
11 Cache is generally implemented as
(a) slow static RAM.
(b) slow dynamic RAM.
(c) fast static RAM.
(d) fast dynamic RAM.
[2 marks]
12 If X and Y are unsigned eight bit numbers, the following 8051 code will
mov A,X
clr C
subb A,Y
jz kkk
jc kkk
(a) jump to the label kkk if X does not equal C
(b) jump to the label kkk if X <= Y
(c) jump to the label kkk if X >= Y
(d) never jump to label kkk as the "clr c" instruction has cleared the carry bit.
[2 marks]
13 After the following 8051 code has executed, what value is in the accumulator?
mov 40h,#$F8
mov r0,#$40
mov a,@r0
anl a,#$1F
(a) 0
(b) $40
(c) 8
(d) $18
[2 marks]
14 Both polling and interrupts can be used for controlling I/O devices. Which of the following statements is correct?
(a) Polling systems always have slower response times than interrupt-driven systems.
(b) The stack must be initialised before polled I/O control can be used.
(c) The hardware status bits necessary for polled I/O are sometimes necessary when interrupts are used for device control.
(d) Polling systems are the most suitable when a large number of devices need to be controlled as the simplicity of the software makes a predictable and rapid response time easy to achieve.
[2 marks]
SECTION B (long answers)
Three Questions – each worth 24 marks
Answer questions 15 to 17 in the Blue Answer Booklet provided.
Write the numbers of the questions you have answered from this Section on the front cover of your blue answer booklet.
Do NOT tie the Scantron Card into your Blue Answer Booklet.
15 (a) Describe (or draw a diagram showing) how the fields in an IEEE 754 single-precision (32-bit) floating point number are allocated, and explain how the sign, exponent and significand (mantissa) are combined to produce the numerical value of the number.
[6 marks]
(b) Draw a diagram showing the general format of an ASM (Algorithmic State Machine) circuit, and explain briefly how this type of circuit operates.
[6 marks]
(c) Draw a block diagram that shows the datapath associated with a MIPS register-type instruction, and describe, with the help of the diagram, the data transfers that occur. You are not required to work at the bit-slice level (so don’t draw the components of any ALUs, for example), and parts of the architecture that are required for other activities such as address calculation, memory access instructions, instruction fetching are not required and their inclusion may result in a reduced mark.
[6 marks]
(d) A pipelined architecture without any pipeline optimisation has 8 stages and a 20ns clock. Without the pipeline, a single-cycle version of the architecture takes 170ns per instruction. It has been determined that when the pipeline is in operation, it is able to process, on average, 10 instructions before having to be flushed.
What is the speedup of the pipelined architecture over the non-pipelined architecture?
Notes: You may find that drawing a diagram will clarify the timing.
The calculation is very simple; but if you wish, you may express the result as a ratio, without loss of marks.
[6 marks]
16 (a) The diagram below shows how cache miss rate varies as the block size increases. There are four separate traces.
Explain why the general trend from left to right is downwards, and explain why there is an upwards tilt at the right hand end of the traces for the smallest caches.
[6 marks]
(b) Write down two implications of the fact that page faults causes delays of millions of clock cycles.
[6 marks]
(c) You're responsible for the design of cache for a new processor.
Specify, giving reasons, which combination of the following caching techniques would be most suitable for level 1 cache and for level 3 cache.
Placement policy: direct mapping and set-associative mapping.
Replacement update policy: FIFO and LRU
[6 marks]
(d) Explain, using a diagram to illustrate your explanation, how a page table register, a page table and a virtual address are used in a Virtual Memory system to produce a physical address.
[6 marks]
17 (a) The 8051 status register contains the following bits.
CY – AC - F0 - RS1 - RS0 – OV - F1 - P
Briefly describe the purpose of each bit and when it is set and/or reset.
[4 marks]
(b) Show how the following code fragments could be translated into 8051 assembler.
A literal translation is not required, just code that implements the same functionality.
(i) The variables X and Y are one byte variables …
X = X * 29 – Y;
[2 marks]
(ii) Assume byte is a data type and the array M is stored in a data memory starting
at location $50 …
for (byte x = 4; x <= $1F; x++)
M[x] = $FF;
[3 marks]
(iii) The following is a pseudo-code fragment to build a string from characters entered by the user.
Assume:
- a getch() subroutine exists and returns a character in the accumulator.
- the character array myString starts at location $50 in data memory
byte ch = getch();
byte i = 0;
repeat
myString[i] = ch; // myString starts at Data Memory location $50
i = i+1;
ch = getch();
until ((ch == '.') || (ch == ';'));
[5 marks]
(c) Describe what interrupts are, why they might be useful, and what (if any) setup
is necessary before they can be used.
[4 marks]
Question 17 continued over…
Question 17 continued…
(d) Write a subroutine to add two multi-byte numbers (N1 and N2). On entry to the subroutine:
r0 contains the address of the first (the least significant) byte of the first number (N1)
r1 contains the address of the first byte of the second number (N2)
r7 contains the number of bytes in each number (they're the same)
The numbers are stored so that the least significant byte is stored at the specified memory address and higher-order bytes are stored in consecutive memory locations in ascending address order.
The multi-byte result of the addition is stored in the same memory as N2.
Demonstrate the use of your subroutine by showing the instructions necessary to
add two 3 byte numbers starting at $20 and $30.
[6 marks]
+ + + + + + + +
8051 Architecture Reference
Program Counter: 16 bit register restricted to 0000H -> 07FFFH
Special Function Registers (SFR) Space:
Byte address / Name / Description / Bits("-" Þ NOT bit addressable)
80H / P0 / Port 0 / bit addressable: P0.7 -> P0.0
81H / SP / Stack Pointer / -
82H / DPL / Low byte of DPTR / -
83H / DPH / High byte of DPTR / -
87H / PCON / Power control / -
88H / TCON / Timer control / TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT0
89H / TMOD / Timer mode control / -
8AH / TL0 / Timer 0 low byte / -
8BH / TL1 / Timer 1 low byte / -
8CH / TH0 / Timer 0 high byte / -
8DH / TH1 / Timer 1 high byte / -
90H / P1 / Parallel port 1 / Bit Addressable P1.7 -> P1.0
98H / SCON / Serial control / SM0-SM1-SM2-REN-TB8-RB8-TI -RI
99H / SBUF / Serial buffer / -
A0H / P2 / Port 2 / Bit addressable: P2.7-P2.0
A8H / IE / Interrupt Enable / EA - - -ES -ET1-EX1-ET0-EX0
B0H / P3 / Parallel port 3 / Bit addressable: P3.7 -> P3.0
B8H / IP / Interrupt priority / - - -PS -PT1-PX1-PT0-PX0
D0H / PSW / Program Status Word / CY -AC -F0 -RS1-RS0-OV -F1 -P
E0H / ACC / Accumulator / ACC.7 -> ACC.0
F0H / B / B register / B.7 -> B.0
Interrupt control register