DIGITAL DESIGN COEN 312 Drs

Question 1

(1)Design a 3-8 decoder using NAND gates only. Mark the outputs with their corresponding binary values. (3 marks)

(2)Use a 3-8 decoder plus minimal extra logic gates to implement the following functions: (3 marks)

F1(A,B,C) =  m(0,1,2)

F2(A,B,C) =  m(3,4,5)

F3(A,B,C) =  m(5,6,7)

(3)Use a 4-1 MUX plus minimal extra logic gates to implement the following function: (4 marks)

F4(A,B,C,D)=A’B’ + ABC’ + AB’D

Question 2

(1)Design a circuit that multiplies two 2-bit binary numbers A = a1a0 and B = b1b0

(6 marks)

(2)What size of ROM is required to implement the above multiplier? (2 marks)

(3)Give the circuit implementation of the above ROM and its ROM truth table.

(2 marks)

Question 3

(1)What is the difference between ROM, PLA, and PAL? (2 marks)

(2)Design a minimal size PLA that implements a full adder. Draw the PLA circuit diagram. Show the places the PLA is programmed by clear dots. (8 marks)

Question 4

Design a counter that counts through the sequence of odd numbers between 0 and 15,

i.e., the sequence of 1, 3, 5, …, 15, and back to 1. (10 marks)

Question 5

(1)Derive the transition table of the RS flip-flop. (2 marks)

(2)Implement the D flip-flop using the RS flip-flop, following the sequential circuit design process. (4 marks)

(3)Implement the JK flip-flop using D flip-flop. (3 marks)

Question 6

(1)Analyze the following sequential circuit and derive its state table and state diagram. (6 marks)

(2)A sequential circuit has a state diagram as shown in Figure 2. Derive the equivalent state diagram with minimum number of states for the sequential circuit. Show the process. (5 marks)

Solutions

Question 1

(1)

Invert outputs if positive logic was required.

(2)

(3) F4(A,B,C,D)=A’B’ + ABC’ + AB’D

Question 2

(1)

M3 =  m(15) = a1a0b1b0 (Equ. 1)

M2 =  m(10, 11, 14) M1 =  m(6,7,9,11,13,14)

= a1a0’b1 + a1b1b0’ = a1b1’b0 + a1’a0b1

(Equ. 2) + a1a0’b0 + a0b1b0’

(Equ. 3)

M0 =  m(5,7,13,15)

= a0b0 (Equ. 4)

(2) Size of the ROM is 16 words of 4 bits/word = 64 bits

(3)

Tabular form

Circuit Diagram

Question 3

There are regular AND-OR Arrays.

(1)A ROM has fixed AND gates which generates all possible miniterms (decoder) and programmable OR gates which are programmed depending on the implementation.

A PAL is the opposite with programmable AND gates and fixed OR gates.

A PLA has both programmable AND gates and OR gates which gives a much more flexible implementation and saving area and power.

(2)A full adder

Question 4

y3+ = y3y1’ + y3y2’ + y3’y2y1 y2+ = y2y1’ + y2y1

y1+ = y1’ y0+ = 1

This FF is unnecessary and the

line can be connected to ‘1’.

* I f you use 8 states then output must be 4-bits corresponding to the numbers. y0 always 1 which can be generated externally.

Question 5

(1)

(2)

R = D’ S = D

(3)

Question 6

(1)For JK, Q+ =JQ’ +K’Q

Equ. 1:

JA = YB

KA =X’YB

QA+ = JAYA’ +KAYA

= YBYA’ + (X’YB)YA

= YBYA’ + YB’YA + X’YA

QA+ = (YB YA) + xYA

Equ. 2:

JB =y

KB =x  YA

QB+ = JBYB’ +KB’YB

= yYB’ + (x YA)YB

QB+ = yYB’ + YA’x’YB +YAYBx

Equ. 3:

Z = KB

Z = xYA’ + x’YA

Transition Table

(2)

Re-arranging in accordance to the input

Page 1 of 12 A.J. Al-Khalili