Computer Science and Engineering Department

Computer Science and Engineering Department

Digital Logic for Computers (ACOE161)

Assignment

Instructions: Students will do the assignment in pairs, preferably with their laboratory exercise partner.

Question 1: [100 marks]

Design a Linear Feedback Shift Register (LFSR) similar to the one shown in the following diagram.

An LFSR is composed by a number of flip-flops, with each flip-flop Q output connected to the next flip-flop D input to form a chain. Certain Q outputs are XORed together and the XOR output is fed back into the input.

Notice that the XOR operation is between Q2 and Q4 and that the output is fed back to the first D flip-flop D input. Design an LFSR with the taps (locations of signals) that are inputs to the XOR gate correspond to the digits of the registration number of one member of the team. For example, regnum 2345 means Q2Q3Q4Q5 will be fed back to the input, and the LFSR will have 6 flip-flops. The LSR shown above corresponds to registration number 24.

The preset and clear inputs will be used to start the flip-flops from a known value which should be the binary equivalent of the last digit of the regnum of the other design team member. For example, regnum 219 means a «seed»value of in the example of the above circuit that has 5 flip-flops. So Q0 and Q3 should be set, while Q1, Q2 and Q4 should be cleared.

Calculate on paper the circuit state and output for 10 cycles after initialization.

Simulate your design by activating the preset and clear inputs first to initialize the LFSR then deactivate them and let the circuit run for 20 cycles. Verify the operation for the first 10 cycles.

The clock should oscillate between 0 and 1 for 20 cycles. The preset or clear inputs should be activated once at the beginning and the deactivated for 20 cycles.

Finally, look at the output sequence of 1s and 0s. Is there a repeating pattern? Is the circuit suitable for a Pseudo-Random Number Generator (PRNG)?

Question 2:(Design contest)

Design a circuit that compares two 4-bit numbers A, B (, ) and has an output of 1 when A > B, otherwise the output should be 0using logic gates. [1st solution - 40 marks, 2nd -20 marks, 3rd - 10 marks]

(hint: Do not attempt to form a complete truth table, since cases!!!! Instead use the relative weight of the bits).

Instructions:

Assignments will be submitted through the e-learning page, one document per group. Groups will be composed of two designers. Both designers will get the same mark.

Deliverables:

Report with the following sections:

1. Input/output signals(10%)
2. Circuit diagram(30%)
3. Circuit operation(30%)
4. Circuit simulation(including multisim screenshots)(30%)
5. Answer to questions(10% off 4)

Section 1 should include a table of signals with three columns as shown in the following example table:

Section 2 should include a circuit diagram using gates, multiplexers, flip-flops etc. accordingly. If necessary the circuit can be partitioned into blocks such as (control, datapath, etc).

Section 3 should explain the circuit operation in detail.

Section 4 should explain the inputs used to test the circuit (test cases), and show simulation results and comment upon them.

Deadline:

Question 1: End of Easter holidays

Question 2: End of the semester