Chapter 5 Basic Computer Organization and Design

Chapter 5 Basic Computer Organization and Design

Chapter 5 – Basic Computer Organization and Design

Section 5.1 – Instruction Codes

Instruction code: a group of bits that tell the computer to perform a specific operation.

  • The instruction code is an opcode plus additional information, such as a memory address. It is not the micro-operation. In terms of programming, it is closest to a single assembly language instruction.

The simplest way to organize a computer:

  • One processor register: AC (Accumulator).
  • The operation is performed with the memory operand and the content of AC.
  • Instruction code format with two parts: Op. Code + Address.
  • Op. Code: specify 16 possible operations (4 bit).

ExampleClear AC, Increment AC,Complement AC...

  • Address: specify the address of an operand (12 bit).
  • If an operation in an instruction code does not need an operand from memory, the rest of the bits in the instruction(address field) can be used for other purpose (e.g. clear AC. increment AC).
  • Memory: 12 bit = 4096words (Instruction and Data are stored).
  • Store each instruction code(program) and operand (data) in 16-bit memory word.
  • When the second part of the instruction code specifies an operand, the instruction is said to have an immediate operand.
  • Addressing Mode (The mode bit I is 0 for direct address and 1 for an indirect address).
  • One bit of the instruction code is used to distinguish between a direct and an indirect address.
  • The bits in the second part of the instruction designate an address of a memory word in which the address of the operand is found (Pointer).
  • Effective address: Address where an operand is physically located.

Direct Addressing:Occurs when the operand part contains the address of needed data.

1. Address part of IR is placed on the bus and loaded into the AR.

2. Address is selected in memory and its data placed on the bus to be loaded into the DR to be used for requested instructions.

Indirect Addressing:Occurs when the operand contains the address of the address of the needed data.

1. Address part of IR is placed on the bus and loaded into the AR.

2. Address is selected in memory and placed on the bus to be loaded back into the AR.

3. New Address is selected in memoryand its data placed on the bus to be loaded into the DR to be used for requested instructions.

Section 5.2 – Computer Registers

Program Counter (PC):

Holds the address of the next instruction to be read from memory after the current instruction is executed.

Instruction words are read and executed in sequence unless a branch instruction is encountered.

A branch instruction calls for a transfer to a nonconsecutive instruction in the program.

The address part of a branch instruction is transferred to PC to become the address of the next instruction.

To read instruction, memory read cycle is initiated, and PC is incremented by one (next instruction fetch).

Common Bus System:

  • The basic computer has eight registers, a memory unit, and a control unit.
  • Paths must be provided to transfer information from one register to another and between memory and registers.
  • A more efficient scheme for transferring information in a system with many registers is to use a common bus.
  • The connection of the registers and memory of the basic computer to a common bus system are shown in Fig. 5-4.
  • The outputs of six registers and memory are connected to the common bus.
  • Selection variables: The specific output is selected by a MUX (S0, S1, S2). Used to specify a register whose output is connected to the common bus at any given time. To select one register out of 8, we need 3 select variables. For example, if S2S1S0 = 011, the output of DR is directed to the common bus.
  • Control variables: LD, INC, CLR, Write, and Read. Various control variables are used to selectthe paths of information and the operation of the registers.
  • Load input (LD):Enables the input of a register connected to the common bus. WhenLD = 1 for a register, the data on the common bus is read into the register during thenext clock pulse transition.
  • Increment input (INR):Increments the content of a register.
  • Clear input (CLR):Clear the content of a register to zero.
  • When the contents of AR or PC (12 bits) are applied to the 16-bit common bus, the fourmost significant bits are set to zero. When AR or PC receives information from thebus, only the 12 least significant bits are transferred to the register. Both INPR andOUTR use only the 8 least significant bits of the bus.
  • The content of any register can be applied onto the bus and an operation can be performed in the adder and logic circuit during the same clock cycle (DR  AC and AC  DR).

Section 5.3 –Computer Instructions

  • The basic computer has three instruction code formats, as shown in Fig. 5-5.
  • Any instruction is recognized by the computer control from the four bits in positions 12 to 15.

Memory-reference instruction: Uses 12-bit address, 1-bit to specify the addressing mode I and3-bits for the Opcode.

Opcode = 000 to 110 (I=0: 0xxx to 6xxx, I=1: 8xxx to Exxx).

Register-reference instruction: It is recognized by the Opcode 111 with a 0 in the left most bit of the instruction. It specifies an operation on or a test of the AC register.

7xxx (7800 to 7001): CLA, CMA, etc.

Input-output instruction: It is recognized by the Opcode 111 with a 1 in the left most bit of the instruction. The remaining 12-bits are used to specify the type of I/O operation or test performed.

Fxxx(F800 to F040): INP, OUT, ION,etc.

  • Table 5-2 lists the basic computer instructions.

An instruction set is complete if we have sufficient number of instructions in each of the following categories:

1. Arithmetic, logic and shift instructions.

2. Instructions for moving data.

3. Program control instructions and check status conditions.

4. Input and output instructions.

Section 5.4 – Timing and Control

  • The timing for all the registers in the basic computer is controlled by a master clock generator.
  • The clock pulses do not change the state of a register unless the register is enabled by a control signal.
  • The control signals are generated in the control unit and provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator.
  • The two major types of control organization are hardwired control and microprogrammed control.
  • The control logic in hardwired control is implemented with gates, flip-flops, decoders, and other digital circuits, where as in microprogrammed control the control information is stored in a control memory, and the control memory is programmed to initiate the required sequence of microoperations.
  • The block diagram of a control unit is shown in Fig. 5-6:

Control Unit Hardware:

Control unit = Control logic gates + 3 × 8 decoder + Instruction register + 4 × 16 decoder + 4-bit sequence counter.

Inputs to the control unit come from IR where an instruction read from the memory unit is stored.

A3 × 8 decoder is used to decode the Opcode bits 12-14 into signals D0, ..., D7.

A 4-bit binary sequence counter (SC) is used to count from 0 to 15 to achieve time sequencing.

A 4 × 16 decoder is used to decode the output of the sequence counter into 16 timing signals, T0, ..., T15. The counter can be cleared to 0, causing the next active timing signal to be T0.

A flip-flop (I) is used to store the addressing mode bit of IR.

A digital circuit with control logic gates and having inputs D0, ..., D7, T0, ..., T15, I, and address bits (11-0 of IR) to generate control outputs supplied to control inputs and select signals of the registers and the bus.

  • The timing diagram of Fig. 5-7 shows the time relationship of the control signals.
  • In Fig. 5-7 the sequence counter is cleared when D3T4 =1 (D3T4: SC  0)

Section 5.5 – Instruction Cycle

  • A program is executed in the computer by going through a cycle for each instruction.
  • In the basic computer each instruction cycle consists of the following phases:

Fetch an instruction from memory.

Decode the instruction.

Read the effective address from memory if the instruction has an indirect address.

Execute the instruction.

  • After step 4, the control goes back to step 1 to execute the next instruction. This process continues until a HALT instruction is encountered.
  • The fetch & decode phases of the instruction cycle consists of the following microoperations synchronized with the timing signals (clocking principle).

Fetch and Decode:

  • Initially, the PC register is loaded with the address of the first instruction in the program.
  • The sequence counter SC is cleared to 0, providing a timing signal T0. After each clock T0, T1, T2, and so on.
  • The microoperations for the fetch and decode phases can be specified by the following register transfer statements.

T0:AR  PC

T1:IR M[AR], PC  PC + 1

T2:D0, ..., D7 Decode IR(12-14), AR  IR(0-11), I IR(15)

  • T0: Since only AR is connected to the address inputs of memory, the address of instruction is transferred from PC to AR.

1. Place the content of PC onto the bus by making the bus selection inputs S2S1S0 = 010.

2. Transfer the content of the bus to AR by enabling the LD input of AR

(AR  PC).

  • T1: The instruction read from memory is then placed in the instruction register IR. At the same time, PC is incremented to prepare for the address of the next instruction.

1. Enable the read input of the memory.

2. Place the content of memory onto the bus by making the bus selection inputs S2S1S0 = 111. (Note that the address lines are always connected to AR, and we have already placed the next instruction address in AR.)

3. Transfer the content of the bus to IR by enabling the LD input of IR

(IR  M[AR]).

4. Increment PC by enabling the INR input of PC (PC PC + 1).

  • T2: The operation code in IR is decoded; the indirect bit is transferred to I, and the address part of the instruction is transferred to AR.
  • Fig. 5-8 shows the register transfers for the fetch phase at T0 and T1. Similar circuits are used to realize the microoperations at T2.

Determine the type of Instruction:

  • At T3, microoperations which take place depend on the type of instruction read from memory.
  • Fig. 5-9 presents an initial configuration for the instruction cycle and shows how the control determines the instruction type after decoding.
  • The four different paths are symbolized as follows, where the control functions must be connected to the proper inputs to activate the desired microoperations.

D7’IT3:AR  M[AR], indirect memory transfer.

D7’I’ T3:Nothing, direct memory transfer.

D7I’ T3:Execute a register-reference instruction.

D7I T3:Execute an I/O instruction.

  • The sequence counter SC must be incremented when D7’T3 = 1, so that the execution of the memory-reference instruction takes place with the next timing variable T4, after which SC is cleared to 0 and control returns to fetch phase with T0 = 1.

Register-Reference Instructions:

  • The 12 register-reference instructions are recognized by I = 0 and D7 = 1 (IR(12-14) = 111).
  • These instructions use bits IR(0-11) of the instruction code to specify one of 12 instructions.
  • Each operation is designated by the presence of 1 in one of the bits in IR(0-11). Therefore D7I’T3 = r is common to all register-transfer instructions.
  • The control function for CLA can be written as D7I’T3B11= rB11.

Section 5.6 – Memory-Reference Instructions

  • Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6) are used to select one of the memory-reference instructions.
  • The execution of these instructions starts with timing signal T4.
  • The AND instruction performs a bit-wise logical AND.
  • The ADD instruction performs a regular addition.
  • The LDA and STA are regular load and store instructions.
  • The BUN (branch unconditional) is a jump instruction.
  • The BSA is used to call subroutines in the basic computer.
  • The ISZ instruction is used for program loops.

Section 5.7 – Input-Output and Interrupt

  • Input Register(INPR), Output Register(OUTR): These two registers communicate with a communication interface serially and with the AC in parallel. The registers have 8 bits and hold an alphanumeric code.
  • Input Flag(FGI), Output Flag(FGO): 1-bit control flip-flops.

FGI: set when INPR is ready, clear when INPR is empty.

FGO: set when operation is completed, clear when output device is in the process of printing.

Input-Output Instructions:

  • Each operation is designated by the presence of 1 in one of the bits in IR(6-11). Therefore D7IT3 = p is common to all input-output instructions.
  • The control function for OUT can be written as D7IT3B10= pB10.
  • The SC is cleared to 0 when D7IT3 = p = 1.

Program Interrupt:

  • The difference of information flow rate between the computer and the input-output device makes programmed control transfer inefficient.
  • The external device informs the computer when it is ready for transfer.
  • When the IEN flip-flop is set to 1, the computer can be interrupted.

Interrupt Cycle:

  • The condition for setting flip-flop R = 1 can be expressed by the following register transfer statement:

T0’T1’T2’(IEN)(FGI + FGO): R  1

  • For the modified fetch and decode phase we will AND the timing signals T0, T1, T2 with R’ so that the fetch and decode phases will be recognized from three control functions R’T0, R’T1, and R’T2.
  • The control will go through a fetch phase only if R = 0, otherwise if R = 1, the control will go through an interrupt cycle.

RT0: AR  0, TR  PC

RT1: M[AR]  TR, PC  0

RT2: PC  PC + 1, IEN  0, R  0, SC  0

Section 5.8 – Complete Computer Description

  • The final flowchart for computer operation:
  • The control functions and microoperations for the basic computer:

Section 5.9 – Design of Basic Computer

  • The basic computer consists of the following hardware components

1. A memory unit with 4096 words of 16bits.

2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC.

3. Seven flip-flops: I, S, E, R, IEN, FGI, and FGO.

4. Two decoders in control unit: 3 × 8 operation decoder, 4 × 16 timingdecoder.

5. A 16-bit common bus.

6. Control logic gates.

7. Adder and logic circuit connected to the AC input

Control Logic Gates:

  • The inputs to this circuit come from the two decoders, the I flip-flop, and bits 0-11 of IR. The other inputs are bits 0-15 of AC to check if AC = 0 and to detect the sign bit AC(15); bits 0-15 of DR to check if DR = 0; and the values of seven flip-flops.
  • The outputs of the control logic circuit are:

1. Signals to control the inputs of the nine registers

2. Signals to control the read and write inputs of memory

3. Signals to set, clear, or complement the F/Fs

4. Signals for S2 S1 S0 to select a register for the bus

5. Signals to control the AC adder and logic circuit

Control of Registers and Memory:

  • Suppose that we want to derive the gate structure associated with the control inputs of AR. We scan Table 5-6 to find all the statements that change the content of AR:

R’T0: AR  PC

R’T2: AR IR(0-11)

D7’IT3: AR M[AR]

RT0: AR  0

D5T4: AR  AR + 1

  • The control functions can be combined into three Boolean expressions as follows:

LD(AR) = R’T0 + R’T2 + D7’IT3

CLR(AR) = RT0

INR(AR) = D5T4

The control logic gate associated with AR is shown in Fig. 5-16.

  • Similarly we can derive the control gates for other registers as well as the logic needed to control the read and write inputs of memory. The read operation is recognized by the symbol M[AR].

Read = R’T1 + D7’IT3 + (D0 + D1 + D2 + D6)T4

Control of Single Flip-flops:

IEN may change as a result of the two instructions ION and IOF.

pB7: IEN  1

pB6: IEN  0

Moreover, at the end of the interrupt cycle IEN is cleared to 0.

RT2: IEN  0

Control of Common Bus:

  • The 16-bit common bus shown in Fig. 5-4 is controlled by the selection inputs S2, S1, S0.
  • Table 5-7 specifies the binary numbers for S2S1S0 that select each register, and it is recognized as the truth table of a binary encoder.
  • Each binary number is associated with a Boolean variable x1 through x7, corresponding to the gate structure that must be active in order to select the register or memory for the bus.
  • The Boolean functions for the encoder are:

S0 = x1 + x3 + x5 +x7

S1 = x2 + x3 + x6 +x7

S2 = x4 + x5 + x6 +x7

  • For example to find the logic that makes x1 = 1, we scan all the register transfer statements in Table 5-6 and extract those statements that have AR as a source.

D4T4: PC  AR

D5T5: PC  AR

x1 = D4T4 + D5T5

  • Similarly

x7 = R’T1 + D7’IT3 + (D0 + D1 + D2 + D6)T4

Section 5.10 – Design of Accumulator Logic

  • In order to design the logic associated with AC, it is necessary to extract all the statements that change the content of AC from Table 5-6.

Control of AC Register:

  • The gate structure that controls the LD, INR, and CLR inputs of AC is shown in Fig. 5-20.

Adder and Logic Circuit:

  • The adder and logic circuit can be subdivided into 16 stages; with each stage corresponding to one bit of AC. Figure 5-21 shows one such AC register.
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