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Background Statement for SEMI Draft Document 5965
REAPPROVAL OF SEMI E15-0698E2 (REAPPROVED 0310) SPECIFICATION FOR TOOL LOAD PORT
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this Document.
Notice: Recipients of this Document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.
Background
Per SEMI Regulations 8.9.1, the Originating TC Chapter shall review its Standards and decide whether to ballot the Standards for reapproval, revision, replacement, or withdrawal by the end of the fifth year after their latest publication or reapproval dates.
The NA PIC TC Chapter reviewed and recommended to issue for reapproval ballot.
Per SEMI Procedure Manual (NOTE 19), a reapproval Letter Ballot should include the Purpose, Scope, Limitations, and Terminology sections, along with the full text of any paragraph in which editorial updates are being made.
Voter requests for access to the full Standard or Safety Guideline must be made at least three business days before the voting deadline. Late requests may not be honored.
Review and Adjudication Information
Task Force Review / Committee AdjudicationGroup: / Global PIC Maintenance TF / PIC NA TC Chapter
Date: / April 5, 2016 / April 6, 2016
Time & Timezone: / 2:00-3:00 PM PDT / 9:00 AM -12:00 PM PDT
Location: / Intel / Intel
City, State/Country: / Santa Clara, CA/USA / Santa Clara, CA/USA
Leader(s)/Authors: / Larry Hartsought (U A Associates) / MattFuller (Entegris)
Stefan Radloff (Intel)
Standards Staff: / Laura Nguyen ( ) / Laura Nguyen ( )
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact the task force leaders or Standards staff for confirmation.
Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to attend these meetings in person but would like to participate by telephone/web, please contact Standards staff.
Check on calendar of event for the latest meeting schedule.
SEMI Draft Document 5965
REAPPROVAL OF SEMI E15-0698E2 (REAPPROVED 0310) SPECIFICATION FOR TOOL LOAD PORT
1 Purpose
1.1 This standard is intended to unify the interface between process/inspection tools and automated wafer carrier transport systems while maintaining compatibility with human transport.
2 Scope
2.1 This specification deals with the mechanical interface (load port) for wafer carrier transfer between wafer carrier material transport systems, including humans, and wafer fabrication/inspection equipment (tools). The concept defines the placement and orientation of a wafer carrier on a tool to allow reasonable interfacing with mechanized material movement systems without compromising human access to perform the material exchange function.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the users of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.
3 Impact
3.1 Compliance with this specification requires the placement of load ports on tools to specific heights, orientations, and load depths. Restrictions are also placed on clearances to obstructions which may be adjacent to such ports.
4 Referenced Standards and Documents
4.1 SEMIStandards
SEMI E1 — Specification for 3 inch, 100 mm, 125 mm, and 150 mm Plastic and Metal Wafer Carriers
SEMI E19 — Standard Mechanical Interface (SMIF)
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 Definitions
5.1.1 box — a protective portable carrier for a cassette and/or substrate(s).
5.1.2 cassette — an open structure that holds one or more substrates.
5.1.3 cassette centroid — a datum representing the theoretical center of a stack of wafers in a cassette formed by the pocket centerline and the “center” pocket as defined by the location associated with dividing dimension B3 by two (see SEMI E1, Figure 1).
5.1.4 cassette envelope — a rectangular volume with vertical sides which completely contains a cassette, even if the cassette is tilted (see Figure 1).
5.1.5 enclosed load port — a load port with overhead clearance obstructed by the tool.
5.1.6 global orientation — the general orientation of a wafer carrier in a tool; may be vertical or horizontal.
5.1.7 load depth — the horizontal distance from the load face plane to cassette centroid or carrier centroid (see Figures 2 and 3 (D)).
5.1.8 load face plane — the furthest physical vertical boundary plane from cassette centroid or carrier centroid on the side (or sides) of the tool where loading of the tool is intended (see Figures 2 and 3).
5.1.9 load height — the distance from the bottom of the cassette or carrier to the floor at the load face plane (see Figure 3 (H)).
5.1.10 load port — the interface location on a tool where wafer carriers are delivered. It is possible that wafers are not removed from, or inserted into, the carrier at this location.
5.1.11 open load port — a load port with overhead clearance unobstructed by the tool.
5.1.12 pod — a box having a Standard Mechanical Interface (SMIF) per SEMI E19.
5.1.13 spacing — the minimum spacing between centroids (see Figure 2, S).
5.1.14 tool — any piece of semiconductor fabrication or inspection equipment designed to process wafers delivered in wafer carriers.
5.1.15 tilt — a small angle of offset from the normal horizontal or vertical orientation of a cassette or wafer carrier designed to preferentially align or keep wafers in their intended place within the carrier/cassette (see Figure 1, T).
5.1.16 wafer carrier — any cassette, box, pod, or boat that contains wafers.
5.1.17 wafer carrier centroid — a datum representing the theoretical location of the center of a stack of wafers in the carrier.
5.1.18 wafer carrier envelope — a rectangular volume with vertical sides which completely contains a carrier, even if the carrier is tilted (see Figure 1).
5.2 Description of Terms Specific to thisStandard
5.2.1 carrier — wafer carrier.
NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the user. Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change without notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline. Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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