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B.Tech VLSI 2016-2017 Projects
Front End Design(VHDL/Verilog HDL)S.No / Project Name / IEEE Year
1 / A review on power optimized TPG using LP-LFSR for low power BIST / 2016
2 / A Modified Partial Product Generator for Redundant Binary Multipliers / 2016
3 / Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units / 2016
4 / Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block / 2016
5 / Low power area efficient ALU with low power full adder / 2016
6 / Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes / 2016
7 / Pipeline and parallel processor architecture for fast computation of 3D-DWT using modified lifting scheme / 2016
8 / VLSI Implementation of a Key Distribution Server Based Data Security Scheme for RFID System / 2016
9 / FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption / 2016
10 / Carry speculative adder with variable latency for low power VLSI / 2016
11 / Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint / 2016
12 / Interfacing Synchronous and Asynchronous Domains for Open Core Protocol / 2016
13 / VLSI design of high speed Vedic Multiplier for FPGA implementation / 2016
14 / Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter / 2016
15 / A novel SOLS technique for reducing area and achieving better HUR of FM0/Manchester encoding in DSRC application / 2016
16 / High - Throughput Finite Field Multipliers Using Redundant Basis For Fpga And Asic Implementations / 2015
17 / A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT / 2015
18 / Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes / 2015
19 / Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures / 2015
20 / Obfuscating Dsp Circuits Via High-Level Transformations / 2015
21 / Low-Power And Area-Efficient Shift Register Using Pulsed Latches / 2015
22 / An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis / 2015
23 / Low-Power Programmable PRPG With Test Compression Capabilities / 2015
24 / Fault Tolerant Parallel Filters Based On Error Correction Codes / 2015
25 / A Synergetic Use Of Bloom Filters For Error Detection And Correction / 2015
26 / Area-Delay Efficient Binary Adders in QCA / 2014
27 / Implementation of JPEG2000 using DWT / 2014
28 / Design and implementation of efficient Quaternary Signed Digit Multiplier / 2014
29 / Multi bit Flip-Flop design for Area efficiency / 2014
30 / Single phase clock distribution using VLSI technology for low power / 2014
31 / High Speed FPGA implementation of FIR Filters for DSP Applications / 2014
32 / Implementation of an Efficient Multiplier based on UrdhvaTiryakbhyam Sutra / 2014
33 / Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA / 2014
34 / Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique / 2014
35 / LUT Optimization for Memory-Based Computation / 2014
36 / A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth Algorithm / 2014
37 / A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by Using Spurious Power Suppression Technique / 2014
38 / Using Self-Immunity Technique 64-bit Register File Immunity Improvement / 2014
39 / High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based wavelet Transform / 2014
40 / Bar Code Reader(RFID Gun) with Reliable and Higher Throughput Anti-Collision Technique / 2014
41 / Constant and high speed adder design using QSD number system / 2014
42 / FPGA implementation of multi operand redundant adders / 2014
43 / A Novel Approach for parallel CRC generation for High Speed Application / 2014
44 / Platform-Independent Customizable UART Soft-Core / 2014
45 / A Common Boolean Logic(CBL) implementation for modified CSLA / 2014
46 / Implementation of Bus Bridge between AHB and OCP / 2014
47 / An Efficient Implementation of Floating Point Multiplier / 2014
48 / A New Approach To Design Fault Coverage Circuit With Efficient Hardware Utilization for Testing Applications / 2014
49 / Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR Algorithm / 2014
Back End Design
50 / Recursive Approach To The Design Of A Parallel Self-Timed Adder / 2015
51 / Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks / 2015
52 / Design of Secure Differential Logic Gates for DPA Resistant Circuits for High-Secure Applications / 2014
53 / Pulse Triggered Flip-Flop Design for low power / 2014
54 / Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm technology / 2014
55 / Statistical Analysis of MUX-Based Physical Unclonable Functions / 2014
56 / Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator / 2014
57 / Digitally Controlled Pulse Width Modulator for On-Chip Power Management / 2014
58 / A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO / 2014
59 / Area Efficient ROM-Embedded SRAM Cache / 2014
60 / A Low Power MICS Band Phase - Locked Loop for High Resolution Retinal Prosthesis / 2014
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