EO213 10 /10
SCHOOL OF ENGINEERING
MODULAR HONOURS DEGREE COURSE
LEVEL 2
SEMESTER 2
2005/2006
DIGITAL DESIGN
Examiner: Mr. C.S. Knight
Attempt ALL questions in Section A Time allowed: 2 hours
Attempt TWO questions in Section B
Total number of questions = 11
Section A - Carries 50 marks. Note that not all questions carry the same marks.
Section B - Each question carries 25 marks.
The figures in brackets indicate the relative weightings of parts of a question.
Special Requirements: PALCE16V8 Data
SECTION A
1) Part of a digital system contains a PALCE16V8-7JC chip. A data sheet for this device is supplied.
For this chip, determine the following:
a) The maximum voltage for a logic '0' output.
b) The minimum voltage that would be guaranteed to be recognised as a logic '1' input.
c) The worst-case noise margin.
d) The maximum current drawn from the supply under ‘normal’ operating conditions.
e) The maximum propagation delay. (5)
2) For the PALCE16V8 of question 1;
a) State:
i) the maximum number of possible outputs available and
ii) the number of product terms available for each output. Explain what is meant by ‘product term’ as applied to Boolean algebra.
b) A designer has used a 16V8 to implement a simple synchronous mod 13 binary down counter with a set input. Extra functionality is now required from this chip to implement a combinational logic circuit with a single output, as well as the counter. How many inputs are available for the combinational logic? (6)
3) a) A basic VHDL description has three fundamental sections. Name these sections.
b) Briefly define the term “std_logic_vector” and explain where and how it might be used. (5)
4) a) State and explain the main disadvantage associated with asynchronous sequential designs when compared to synchronous designs.
b) A simple synchronous sequential circuit uses a PALCE16V8-7JC. From the data sheet given for this device find:
i) the hold time,
ii) the set-up time and
iii) the feedback propagation delay for the internal flip-flops.
Hence determine the maximum clock frequency that could be used for this circuit. (5)
5) An uncommented VHDL description of a simple circuit element is given below.
library ieee;
use ieee.std_logic_1164.all;
entity q5 is port
(ch: in std_logic_vector(2 downto 0);
I: in std_logic_vector(7 downto 0);
O: out std_logic;
ce: in std_logic);
end q5;
architecture module1 of q5 is
begin
process (ch,I)
begin
if ce= ‘1’ then O<= ‘Z’;
elsif ch="000" then O<=I(0);
elsif ch="001" then O<=I(1);
elsif ch="010" then O<=I(2);
elsif ch="011" then O<=I(3);
elsif ch="100" then O<=I(4);
elsif ch="101" then O<=I(5);
elsif ch="110" then O<=I(6);
elsif ch="111" then O<=I(7);
end if;
end process;
end module1;
a) Describe and name the precise function of this circuit element.
b) Briefly describe how this circuit works.
c) In the above VHDL code, single quote marks (e.g. ‘1’) and double quote marks (e.g. “011”) are used. Explain when each of these notations should be implemented. (7)
6) Given below is an incomplete VHDL description for a synchronous, mod 6 down counter with a clear input. Complete the architecture section of this design such that the appropriate function is achieved. State any assumptions made.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
bout: inout unsigned(2 downto 0);
clk, clr: in std_logic );
end counter;
architecture mod6_down of counter is
begin
count: process (clk, clr)
variable temp :unsigned(2 downto 0);
begin
///////////////////////////
// Missing Code //
///////////////////////////
end process count;
end mod6_down; (8)
7) The simulation output of a VHDL design for a particular circuit is provided below. 'clk', ‘shld’ and 'bin' are binary inputs and 'sout' is a binary output.
a) Calculate the simulation clock frequency.
b) State the precise function of this circuit and explain how it works.
c) Briefly explain what type of ‘stimulators’ may have been used for each of the inputs. (7)
8) The following is a VHDL description of a 2-bit asynchronous binary down counter. The code contains 6 errors.
a) Identify these errors and show how they may be corrected.
b) Detail the modifications required to change this design to a 2-bit asynchronous binary up counter.
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity two_bit_async is port
5 (clock0, clear : in std_logic;
6 Q0: in std_logic
7 Q1: out std_logic);
8 end two_bit_async;
9
10 architecture example of two_bit_async is
11 begin
12 process (clock0,Q0,Q1,clear)
13 variable state0, state1: std_logic;
14 begin
15 -- Stage 0
16 if clear = '0' then
17 state0 := '0';
18 elsif rising_edge then
19 state0 := not state0;
20 end;
21 Q0 <= state1 after 10 ns;
22 -- Stage 1
23 if clear = '0' then
24 state1 := '0';
25 elsif rising_edge (Q0) then
26 state1 := not state1;
27 end if;
28 Q1: = state1 after 10 ns;
29 end process;
30 end example;
(7)
SECTION B
9) A diagram of a ring counter is given below in Fig Q9.
a) From the circuit, derive a state diagram that fully describes the circuit function. (7)
b) From the state diagram, draw up waveforms for E, F and G with respect to the clock input. (7)
c) Given below is an incomplete VHDL description of this circuit. Complete the design by writing the VHDL code for the architecture.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ring_counter is port (
bout: inout unsigned(2 downto 0);
clk : in std_logic );
end ring_counter;
(11)
10) A synchronous sequence generator is required as part of a large digital system. The generator is to be self-starting and has the following inputs and outputs:
· clk – clock input, rising-edge triggered.
· bout – a 3-bit binary output.
The required binary sequence is as follows: 001, 010, 101, 110, 111, 100. This sequence is then repeated.
a) Write a complete VHDL description for the sequence generator that could be used to implement the design on a 16V8 PLD. (18)
b) Modify your design such that an extra input ‘dir’ controls the direction of the generated sequence. State any assumptions made. (7)
11) The control electronics for a Coca-Cola vending machine is to be designed for use in the Federal Republic of Belchers. Belchers has a monetary system with only two coins; a 1-credit coin and a 2-credit coin.
Coca-Cola is to be sold from the machine at a cost of 4 credits per bottle. Change of 1 credit is to be given when appropriate.
The electronic control is to be implemented with a simple synchronous state machine that uses 74 HCT series chips. A block diagram is given below.
a) Draw a state diagram for the Moore model of the control circuit. (12)
b) From the Moore model, determine the present/next state table and hence derive
minimised equations for implementing this function with your choice of flip-flops. (13)